40-Channel, 3 V/5 V, Single-Supply, 12-Bit, denseDAC® AD5381 Data Sheet FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic INL error: ±1 LSB max On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: –40°C to +85°C Rail-to-rail output amplifier Power-down Package type: 100-lead LQFP (14 mm × 14 mm) User interfaces: Parallel Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible, featuring data readback) I2C®-compatible Robust 6.
AD5381 Data Sheet TABLE OF CONTENTS General Description ......................................................................... 3 Asynchronous Clear Function.................................................. 25 Specifications..................................................................................... 4 BUSY and LDAC Functions...................................................... 25 AD5381-5 Specifications .............................................................
Data Sheet AD5381 GENERAL DESCRIPTION The AD5381 is a complete, single-supply, 40-channel, 12-bit denseDAC® available in a 100-lead LQFP package. All 40 channels have an on-chip output amplifier with rail-to-rail operation. The AD5381 includes a programmable internal 1.25 V/2.
AD5381 Data Sheet SPECIFICATIONS AD5381-5 SPECIFICATIONS AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications TMIN to TMAX , unless otherwise noted. Table 2.
Data Sheet Parameter LOGIC INPUTS (SDA, SCL ONLY)3 VIH , Input High Voltage VIL, Input Low Voltage IIN , Input Leakage Current VHYST, Input Hysteresis CIN , Input Capacitance Glitch Rejection LOGIC OUTPUTS (BUSY, SDO)3 VOL, Output Low Voltage VOH , Output High Voltage VOL, Output Low Voltage VOH , Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA)3 VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDD D
AD5381 Data Sheet AD5381-3 SPECIFICATIONS AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications TMIN to TMAX , unless otherwise noted. Table 3.
Data Sheet AD5381 Parameter LOGIC OUTPUTS (BUSY , SDO)3 VOL, Output Low Voltage VOH , Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA)3 VOL, Output Low Voltage AD5381-3 1 Unit Test Conditions/Comments 0.4 DVDD – 0.
AD5381 Data Sheet TIMING CHARACTERISTICS SERIAL INTERFACE TIMING DVDD = 2.7 V to 5.5 V; AVDD= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX , unless otherwise noted. Table 5. Parameter 1, 2, 3 t1 t2 t3 t4 t5 4 t6 4 t7 t7A t8 t9 t10 4 t11 t12 4 t13 t14 t15 t16 t17 t18 t19 t20 5 t21 5 t22 5 t23 Limit at T MIN, T MAX 33 13 13 13 13 33 10 50 5 4.
Data Sheet AD5381 t1 24 SCLK t3 t4 t2 24 t5 t6 SYNC t7 t8 t9 DB0 DIN DB23 t10 BUSY t11 t13 t12 t17 LDAC1 t14 VOUT1 t15 t13 LDAC2 t17 t16 VOUT2 t18 CLR t19 03732-003 VOUT 1LDAC ACTIVE DURING BUSY. 2LDAC ACTIVE AFTER BUSY. Figure 3. Serial Interface Timing Diagram (Standalone Mode) SCLK 24 48 t7A SYNC DB23 DIN DB0 DB23 DB0 INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION DB0 UNDEFINED 03732-004 DB23 SDO SELECTED REGISTER DATA CLOCKED OUT Figure 4.
AD5381 Data Sheet I2C SERIAL INTERFACE TIMING DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX , unless otherwise noted. Table 6. Parameter 1, 2 FSCL t1 t2 t3 t4 t5 t6 3 t7 t8 t9 t10 t11 Cb Limit at T MIN, T MAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 300 0 300 20 + 0.
Data Sheet AD5381 PARALLEL INTERFACE TIMING DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX , unless otherwise noted. Table 7. Parameter 1, 2, 3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 4 t10 4 t11 4, 5 t12 t13 t14 t15 t16 t17 t18 t19 t20 Limit at T MIN, T MAX 4.5 4.5 20 20 0 0 4.5 4.
AD5381 Data Sheet t1 t0 REG0, REG1, A5...A0 t4 t5 t2 CS t9 t8 t3 WR t6 t15 t7 DB11...DB0 t10 t11 BUSY t12 t13 t18 LDAC1 t14 VOUT1 t16 LDAC2 t13 t18 t17 VOUT2 CLR t19 1LDAC 2LDAC ACTIVE DURING BUSY. ACTIVE AFTER BUSY. Figure 7. Parallel Interface Timing Diagram Rev.
Data Sheet AD5381 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.1 Table 8.
AD5381 Data Sheet 76 BUSY 75 PIN 1 IDENTIFIER 2 3 4 74 73 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 13 14 AD5381 64 TOP VIEW (Not to Scale) 63 62 15 61 16 60 17 59 18 58 19 57 20 56 21 22 55 23 24 53 52 25 51 50 49 48 47 46 45 44 43 42 41 40 38 39 37 36 35 34 33 32 31 30 29 28 SIGNAL_GND5 DAC_GND5 AGND5 AVDD5 VOUT5 VOUT6 VOUT7 VOUT32 VOUT33 VOUT34 VOUT35 VOUT36 VOUT37 VOUT38 VOUT39/MON_OUT VOUT8 VOUT9 VOUT10 VOUT11 VOUT12 DAC_GND2 SIGNAL_GND2
Data Sheet Mnemonic REFOUT/REFIN VOUT39/MON_OUT SER/PAR CS/(SYNC/AD0) WR /(DCEN/AD1) DB11–DB0 A5–A0 REG1, REG0 SDO/(A/B) BUSY LDAC CLR RESET AD5381 Function The AD5381 contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference output. If the application requires an external reference, it can be applied to this pin and the internal reference can be disabled via the control register. The default for this pin is a reference input.
AD5381 Data Sheet Mnemonic PD Function Power-Down (Level Sensitive, Active High). PD is used to place the device in low power mode, where the analog current consumption is reduced to 2 µA and the digital current consumption is reduced to 20 µA. In power-down mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high impedance output or provides a 100 kΩ load to ground, depending on how the power-down mode is configured.
Data Sheet AD5381 TERMINOLOGY Relative Accuracy Relative accuracy, or endpoint linearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error, and is expressed in LSB. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
AD5381 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.00 1.00 AVDD = 5V REFIN = 2.5V TA = 25°C 0.75 0.50 0.25 0 –0.25 0.25 0 –0.25 –0.50 –0.50 –0.75 –0.75 0 512 1024 1536 2048 2560 INPUT CODE 3072 3584 4096 –1.00 03732-009 –1.00 0 512 Figure 9. Typical AD5381-5 INL Plot 1024 1536 2048 2560 INPUT CODE 3072 3584 4096 03732-012 INL ERROR (LSB) 0.50 INL ERROR (LSB) AVDD = 3V REFIN = 1.25V TA = 25°C 0.75 Figure 12. Typical AD5381-3 INL Plot 1.254 2.
Data Sheet AD5381 AVDD = 5.5V VREF = 2.5V TA = 25°C 14 PERCENTAGE OF UNITS (%) 12 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C 10 VDD 8 6 4 VOUT 9 10 AIDD (mA) 11 03732-102 8 03732-015 2 Figure 15. AI DD Histogram with Boost Off Figure 18. Power-Up Transient 40 DVDD = 5.5V VIH = DVDD VIL = DGND TA = 25°C 10 35 30 FREQUENCY 6 4 25 20 15 10 2 5 0.7 0.8 DIDD (mA) 0.9 1.0 0 –5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0 –4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.
AD5381 Data Sheet 6 6 AVDD = DVDD = 3V VREF = 1.25V TA = 25°C FULL SCALE 5 5 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C 3/4 SCALE 4 3/4 SCALE 2 3 VOUT (V) MIDSCALE 3 VOUT (V) 4 1/4 SCALE FULL SCALE MIDSCALE 2 1 1 ZERO SCALE 0 ZERO SCALE –20 –10 –5 –2 0 2 CURRENT (mA) 5 10 20 40 Figure 21. AD5381-5 Output Amplifier Source and Sink Capability 0.20 –1 –40 03732-021 –1 –40 –10 –5 1/4 SCALE –2 0 2 CURRENT (mA) 5 10 20 –40 Figure 24.
Data Sheet AD5381 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL The AD5381 is a complete, single-supply, 40-channel voltage output DAC that offers 12-bit resolution. The part is available in a 100-lead LQFP package and features both a parallel and a serial interface. This product includes an internal, software selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used to drive the buffered reference inputs; alternatively, an external reference can be used to drive these inputs.
AD5381 Data Sheet ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) Soft CLR The AD5381 contains a number of special function registers (SFRs), as outlined in Table 14. SFRs are addressed with REG1 = REG0 = 0 and are decoded using Address Bits A5 to A0. REG1 = REG0 = 0, A5 to A0 = 000010 DB11 to DB0 = Don’t Care Table 14.
Data Sheet AD5381 Table 15. Control Register Contents MSB CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 LSB CR0 Control Register Write/Read REG1 = REG0 = 0, A5 to A0 = 001100, R/W status determines if the operation is a write (R/W = 0) or a read (R/W = 1). DB11 to DB0 contains the control register data. Control Register Contents CR11: Power-Down Status. This bit is used to configure the output amplifier state in power-down. CR11 = 1. Amplifier output is high impedance (default on power-up).
AD5381 Data Sheet Table 17.
Data Sheet AD5381 HARDWARE FUNCTIONS RESET FUNCTION FIFO OPERATION IN PARALLEL MODE Bringing the RESET line low resets the contents of all internal registers to their power-on reset state. Reset is a negative edgesensitive input. The default corresponds to m at full-scale and to c at zero scale. The contents of the DAC registers are cleared, setting VOUT0 to VOUT39 to 0 V. This sequence takes 270 µs.
AD5381 Data Sheet INTERFACES The AD5381 contains both parallel and serial interfaces. Furthermore, the serial interface can be programmed to be either SPI-, DSP-, MICROWIRE-, or I2C-compatible. The SER/PAR pin selects parallel and serial interface modes. In serial mode, the SPI/I2C pin is used to select DSP-, SPI-, MICROWIRE-, or I2C-interface mode. Figure 3 and Figure 5 show timing diagrams for a serial write to the AD5381 in standalone and daisy-chain modes.
Data Sheet AD5381 Daisy-Chain Mode For systems that contain several devices, the SDO pin can be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. Readback Mode Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. With R/W = 1, Bits A5 to A0, in association with Bits REG1 and REG0, select the register to be read.
AD5381 Data Sheet I2C SERIAL INTERFACE The AD5381 features an I2C-compatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the AD5381 and the master at rates up to 400 kHz. Figure 6 shows the 2-wire interface timing diagrams that incorporate three different modes of operation.
Data Sheet AD5381 SCL SDA 1 0 1 0 1 AD1 AD0 START COND BY MASTER R/W 0 ACK BY AD538x MSB 0 A5 A4 A3 A2 A1 A0 ACK BY AD538x ADDRESS BYTE POINTER BYTE SCL REG1 REG0 MSB LSB MSB LSB ACK BY AD538x ACK BY AD538x MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE STOP COND BY MASTER Figure 31.
AD5381 Data Sheet 2-Byte Mode PARALLEL INTERFACE Following initialization of 2-byte mode, the user can update channels sequentially. The device address byte is only required once and the pointer address pointer is configured for autoincrement or burst mode. The SER/PAR pin must be tied low to enable the parallel interface and disable the serial interfaces. Figure 7 shows the timing diagram for a parallel write. The parallel interface is controlled by the following pins.
Data Sheet AD5381 MICROPROCESSOR INTERFACING When data is being transmitted to the AD5381, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the MC68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle.
AD5381 Data Sheet PIC16C6X/7X DVDD AD5381 SER/PAR SDO SDO/RC5 DIN SCK/RC3 SCLK RA1 SYNC SPI/I2C 03732-036 RESET SDI/RC4 Figure 36. AD5381-to-PIC16C6x/7x Interface AD5381 to 8051 The AD5381 requires a clock synchronized to the serial data. The 8051 serial interface must therefore be operated in Mode 0. In this mode, serial data enters and exits through RxD, and a shift clock is output on TxD. Figure 37 shows how the 8051 is connected to the AD5381.
Data Sheet AD5381 POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5381 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board.
AD5381 Data Sheet MONITOR FUNCTION The AD5381 channel monitor function consists of a multiplexer addressed via the interface, allowing any channel output to be routed to this pin for monitoring using an external ADC. In channel monitor mode, VOUT39 becomes the MON_OUT pin, to which all monitored signals are routed. The channel monitor function must be enabled in the control register before any channels are routed to MON_OUT.
Data Sheet AD5381 DATA REGISTER A DAC REGISTER VOUT 12-BIT DAC LDAC CONTROL INPUT A/B 03732-042 DATA REGISTER B INPUT INPUT DATA REGISTER Figure 42. Toggle Mode Function OPTICAL ATTENUATORS UTILIZING FIFO Based on its high channel count, high resolution, monotonic behavior, and high level of integration, the AD5381 is ideally targeted at optical attenuation applications used in dynamic gain equalizers, variable optical attenuators (VOAs), and optical add-drop multiplexers (OADMs).
AD5381 Data Sheet GROUP B CHNLS 40–79 FIFO DATA LOAD GROUP A 1.6µs 1.6µs 14.4µs GROUP C CHNLS 80–119 GROUP D CHNLS 120–159 GROUP E CHNLS 160–199 GROUP F CHNLS 200–239 GROUP G CHNLS 240–279 FIFO DATA LOAD GROUP B GROUP I CHNLS 320–359 FIFO DATA LOAD GROUP J OUTPUT UPDATE TIME FOR GROUP A 14.4µs GROUP H CHNLS 280–319 OUTPUT UPDATE TIME FOR GROUP J OUTPUT UPDATE TIME FOR GROUP B TIME TO UPDATE 400 CHANNELS = 28.8µs Figure 44. Using FIFO Mode 400 Channels Updated in Under 30 µs Rev.
Data Sheet AD5381 OUTLINE DIMENSIONS 16.20 16.00 SQ 15.80 1.60 MAX 0.75 0.60 0.45 100 1 76 75 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY 51 50 25 26 VIEW A 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW 0.27 0.22 0.17 051706-A 1.45 1.40 1.35 COMPLIANT TO JEDEC STANDARDS MS-026-BED Figure 45.
AD5381 Data Sheet NOTES Rev.
Data Sheet AD5381 NOTES Rev.
AD5381 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03732-0-9/12(D) Rev.
