Datasheet

Data Sheet AD5380
Rev. C | Page 21 of 40
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE—GENERAL
The AD5380 is a complete, single-supply, 40-channel voltage
output DAC that offers 14-bit resolution. The part is available
in a 100-lead LQFP package and features both a parallel and a
serial interface. This product includes an internal, software
selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used
to drive the buffered reference inputs; alternatively, an external
reference can be used to drive these inputs. Internal/external
reference selection is via the CR10 bit in the control register;
CR12 selects the reference magnitude if the internal reference
is rail-to-rail output capable of driving 5 kΩ in parallel with a
200 pF load.
03731-027
VOUT
R
R
14-BIT
DAC
DAC
REG
m REG
c REG
×1 INPUT
REG
×
2INPUT DATA
V
REF
AVDD
Figure 27. Single-Channel Architecture
The architecture of a single DAC channel consists of a 14-bit
resistor-string DAC followed by an output buffer amplifier
operating at a gain of 2. This resistor-string architecture guaran-
tees DAC monotonicity. The 14-bit binary digital code loaded
to the DAC register determines at what node on the string the
voltage is tapped off before being fed to the output amplifier.
Each channel on these devices contains independent offset and
gain control registers that allow the user to digitally trim offset
and gain. These registers give the user the ability to calibrate out
errors in the complete signal chain, including the DAC, using
the internal m and c registers, which hold the correction factors.
All channels are double buffered, allowing synchronous updat-
ing of all channels using the
LDAC
pin. Figure 27 shows a block
diagram of a single channel on the AD5380. The digital input
transfer function for each DAC can be represented as
x2 = [(m + 2)/ 2
n
× x1] + (c – 2
n – 1
)
where:
x2 is the data-word loaded to the resistor string DAC.
x1 is the 14-bit data-word written to the DAC input register.
m is the gain coefficient (default is 0x3FFE on the AD5380).
The gain coefficient is written to the 13 most significant bits
(DB13 to DB1) and the LSB (DB0) is zero.
n = DAC resolution (n = 14 for AD5380).
c is the14-bit offset coefficient (default is 0x2000).
The complete transfer function for these devices can be
represented as
VOUT = 2 × V
REF
× x2/2
n
x2 is the data-word loaded to the resistor string DAC. V
REF
is
the internal reference voltage or the reference voltage externally
applied to the DAC REFOUT/REFIN pin. For specified
performance, an external reference voltage of 2.5 V is recom-
mended for the AD5380-5, and 1.25 V for the AD5380-3.
DATA DECODING
The AD5380 contains a 14-bit data bus, DB13 to DB0. Depend-
ing on the value of REG1 and REG0 (see Table 2), this data is
loaded into the addressed DAC input registers, offset (c)
registers, or gain (m) registers. The format data, offset (c), and
gain (m) register contents are shown in Table 11 to Table 13.
Table 10. Register Selection
REG1 REG0 Register Selected
1 1 Input Data Register (x1)
1 0 Offset Register (c)
0 1 Gain Register (m)
0 0 Special Function Registers (SFRs)
Table 11. DAC Data Format (REG1 = 1, REG0 = 1)
DB13 to DB0
DAC Output (V)
11 1111 1111 1111 2 V
REF
× (16383/16384)
11
1111
1111
1110
2 V
REF
× (16382/16384)
10 0000 0000 0001 2 V
REF
× (8193/16384)
10 0000 0000 0000 2 V
REF
× (8192/16384)
01 1111 1111 1111 2 V
REF
× (8191/16384)
00 0000 0000 0001 2 V
REF
× (1/16384)
00 0000 0000 0000 0
Table 12. Offset Data Format (REG1 = 1, REG0 = 0)
DB13 to DB0 Offset (LSB)
11
1111
1111
1111
+8191
11 1111 1111 1110 +8190
10 0000 0000 0001 +1
10 0000 0000 0000 0
01 1111 1111 1111 –1
00 0000 0000 0001 –8191
00 0000 0000 0000 –8192
Table 13. Gain Data Format (REG1 = 0, REG0 = 1)
DB13 to DB0 Gain Factor
11 1111 1111 1110 1
10 1111 1111 1110 0.75
01 1111 1111 1110 0.5
00 1111 1111 1110 0.25
00 0000 0000 0000 0