40-Channel, 3 V/5 V, Single-Supply, 14-Bit, denseDAC® AD5380 Data Sheet FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic INL error: ±4 LSB max On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: –40°C to +85°C Rail-to-rail output amplifier Power down Package type: 100-lead LQFP (14 mm × 14 mm) User interfaces: Parallel Serial (SPI®-, QSPI™-, MICROWIRE™-, DSP-compatible, featuring data readback) I2C®-compatible Robust 6.
AD5380 Data Sheet TABLE OF CONTENTS General Description ......................................................................... 3 Asynchronous Clear Function.................................................. 25 Specifications..................................................................................... 4 BUSY and LDAC Functions...................................................... 25 AD5380-5 Specifications .............................................................
Data Sheet AD5380 GENERAL DESCRIPTION The AD5380 is a complete, single-supply, 40-channel, 14-bit denseDAC® available in a 100-lead LQFP package. All 40 channels have an on-chip output amplifier with rail-to-rail operation. The AD5380 includes a programmable internal 1.25 V/2.
AD5380 Data Sheet SPECIFICATIONS AD5380-5 SPECIFICATIONS AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; External REFIN = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
Data Sheet Parameter LOGIC INPUTS (SDA, SCL ONLY)3 VIH, Input High Voltage VIL, Input Low Voltage IIN, Input Leakage Current VHYST, Input Hysteresis CIN, Input Capacitance Glitch Rejection LOGIC OUTPUTS (BUSY, SDO)3 VOL, Output Low Voltage VOH, Output High Voltage VOL, Output Low Voltage VOH, Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA)3 VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDD DVDD P
AD5380 Data Sheet AD5380-3 SPECIFICATIONS AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
Data Sheet Parameter LOGIC OUTPUTS (BUSY, SDO)3 VOL, Output Low Voltage VOH, Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA)3 VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDD DVDD Power Supply Sensitivity3 ∆Midscale/∆ΑVDD AIDD DIDD AIDD (Power-Down) DIDD (Power-Down) Power Dissipation AD5380 AD5380-3 1 Unit Test Conditions/Comments 0.4 DVDD – 0.
AD5380 Data Sheet TIMING CHARACTERISTICS SERIAL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter 1, 2, 3 t1 t2 t3 t4 t5 4 t6 4 t7 t7A t8 t9 t104 t11 t124 t13 t14 t15 t16 t17 t18 t19 t20 5 t215 t225 t23 Limit at TMIN, TMAX 33 13 13 13 13 33 10 50 5 4.
Data Sheet AD5380 t1 24 SCLK t3 t4 t2 24 t5 t6 SYNC t7 t8 t 9 DB0 DIN DB23 t10 t11 BUSY t13 t12 t17 LDAC1 t14 VOUT1 t15 t13 LDAC2 t17 t16 VOUT2 t18 CLR t19 1LDAC 2LDAC 03731-003 VOUT ACTIVE DURING BUSY. ACTIVE AFTER BUSY. Figure 3. Serial Interface Timing Diagram (Standalone Mode) SCLK 24 48 t7A SYNC DB0 DB23 DIN DB23 DB0 NOP CONDITION INPUT WORD SPECIFIES REGISTER TO BE READ DB0 03731-004 DB23 SDO SELECTED REGISTER DATA CLOCKED OUT UNDEFINED Figure 4.
AD5380 Data Sheet I2C SERIAL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 6. Parameter 1, 2 FSCL t1 t2 t3 t4 t5 t6 3 t7 t8 t9 t10 t11 Cb Limit at TMIN, TMAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 300 0 300 20 + 0.
Data Sheet AD5380 PARALLEL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 7. Parameter 1,2,3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 4 t10 t114 t12 t13 t14 t15 t16 t17 t18 t19 t20 Limit at TMIN, TMAX 4.5 4.5 20 20 0 0 4.5 4.
AD5380 Data Sheet t1 t0 REG0, REG1, A5...A0 t5 t4 t2 CS t9 t8 t3 WR t6 t15 t7 DB13...DB0 t10 t11 BUSY t12 t13 t18 LDAC1 t14 VOUT1 t16 LDAC2 t13 t18 t17 VOUT2 CLR t19 1LDAC 2LDAC ACTIVE DURING BUSY. ACTIVE AFTER BUSY. Figure 7. Parallel Interface Timing Diagram Rev.
Data Sheet AD5380 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted1. Table 8. Parameter AVDD to AGND DVDD to DGND Digital Inputs to DGND SDA/SCL to DGND Digital Outputs to DGND REFIN/REFOUT to AGND AGND to DGND VOUTx to AGND Analog Inputs to AGND Operating Temperature Range Commercial (B Version) Storage Temperature Range JunctionTemperature (TJ MAX) 100-Lead LQFP Package θJAThermal Impedance Reflow Soldering Peak Temperature ESD HBM FICDM 1 Rating –0.3 V to +7 V –0.3 V to +7 V –0.
AD5380 Data Sheet 76 BUSY 75 PIN 1 IDENTIFIER 2 3 4 74 73 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 13 14 AD5380 64 TOP VIEW (Not to Scale) 63 62 15 61 16 60 17 59 18 58 19 57 20 56 21 22 55 23 24 53 52 25 51 50 49 48 47 46 45 43 44 42 40 41 38 39 37 35 36 34 33 32 30 31 29 28 SIGNAL_GND5 DAC_GND5 AGND5 AVDD5 VOUT5 VOUT6 VOUT7 VOUT32 VOUT33 VOUT34 VOUT35 VOUT36 VOUT37 VOUT38 VOUT39/MON_OUT VOUT8 VOUT9 VOUT10 VOUT11 VOUT12 DAC_GND2 SIGNAL_GND2
Data Sheet Mnemonic VOUT39/MON_OUT SER/PAR CS/(SYNC/AD0) WR/(DCEN/AD1) DB13–DB0 A5–A0 REG1, REG0 SDO/(A/B) BUSY LDAC CLR RESET PD AD5380 Function This pin has a dual function. It acts a a buffered output for Channel 39 in default mode. However, when the monitor function is enabled, this pin acts as the output of a 39-to-1 channel multiplexer that can be programmed to multiplex one of Channels 0 to 38 to the MON_OUT pin.
AD5380 Mnemonic FIFO EN DB11/(SPI/I2C) DB12/(SCLK/SCL) DB13/(DIN/SDA) Data Sheet Function FIFO Enable (Level Sensitive, Active High). When connected to DVDD, the internal FIFO is enabled, allowing the user to write to the device at full speed. FIFO is only available in parallel interface mode. The status of the FIFO EN pin is sampled on power-up, and also following a CLEAR or RESET, to determine if the FIFO is enabled. In either serial or I2C interface modes, the FIFO EN pin should be tied low.
Data Sheet AD5380 TERMINOLOGY Relative Accuracy Relative accuracy, or endpoint linearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error, and is expressed in LSB. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
AD5380 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2.0 2.0 AVDD = DVDD = 5.5V VREF = 2.5V TA = 25°C 1.5 1.0 0 –0.5 0.5 0 –0.5 –1.0 –1.0 –1.5 –1.5 0 4096 8192 INPUT CODE 12288 16384 –2.0 03731-009 –2.0 0 Figure 9. Typical AD5380-5 INL Plot 4096 8192 INPUT CODE 12288 16384 03731-012 INL ERROR (LSB) 1.0 0.5 Figure 12. Typical AD5380-3 INL Plot 40 2.510 35 30 FREQUENCY 2.505 2.500 25 20 15 10 2.995 2 4 6 8 10 12 TIME (µs) Figure 10.
Data Sheet AD5380 AVDD = 5.5V VREF = 2.5V TA = 25°C 14 PERCENTAGE OF UNITS (%) 12 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C 10 VDD 8 6 4 VOUT 10 AIDD (mA) 11 03731-102 9 8 03731-015 2 Figure 15. AIDD Histogram with Boost Off Figure 18. AD5380 Power-Up Transient DVDD = 5.5V VIH = DVDD VIL = DGND TA = 25°C 10 14 12 NUMBER OF UNITS 8 6 4 10 8 6 4 2 0.6 0.7 0.8 DIDD (mA) 0.9 1.0 0 –2 –1 0 1 INL ERROR DISTRIBUTION (LSB) 2 Figure 19. INL Distribution Figure 16.
AD5380 Data Sheet 6 6 AVDD = DVDD = 3V VREF = 1.25V TA = 25°C FULL SCALE 5 5 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C 3/4 SCALE 4 3/4 SCALE MIDSCALE 3 2 3 VOUT (V) VOUT (V) 4 1/4 SCALE FULL SCALE MIDSCALE 2 1 1 ZERO SCALE 0 ZERO SCALE –20 –10 –5 –2 0 2 CURRENT (mA) 5 10 20 40 –1 –40 03731-021 –1 –40 Figure 21. AD5380-5 Output Amplifier Source and Sink Capability 0.20 –10 –5 1/4 SCALE –2 0 2 CURRENT (mA) 5 10 20 –40 Figure 24.
Data Sheet AD5380 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL The AD5380 is a complete, single-supply, 40-channel voltage output DAC that offers 14-bit resolution. The part is available in a 100-lead LQFP package and features both a parallel and a serial interface. This product includes an internal, software selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used to drive the buffered reference inputs; alternatively, an external reference can be used to drive these inputs.
AD5380 Data Sheet ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) Soft CLR The AD5380 contains a number of special function registers (SFRs), as outlined in Table 14. SFRs are addressed with REG1 = REG0 = 0 and are decoded using Address Bits A5 to A0. REG1 = REG0 = 0, A5 to A0 = 000010 DB13 to DB0 = Don’t Care Table 14.
Data Sheet AD5380 Table 15. Control Register Contents MSB CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 LSB CR0 Control Register Write/Read REG1 = REG0 = 0, A5 to A0 = 001100, R/W status determines if the operation is a write (R/W = 0) or a read (R/W = 1). DB13 to DB0 contains the control register data. Control Register Contents CR13: Power-Down Status. This bit is used to configure the output amplifier state in power down. CR13 = 1.
AD5380 Data Sheet Table 17.
Data Sheet AD5380 HARDWARE FUNCTIONS RESET FUNCTION FIFO OPERATION IN PARALLEL MODE Bringing the RESET line low resets the contents of all internal registers to their power-on reset state. Reset is a negative edgesensitive input. The default corresponds to m at full scale and to c at zero scale. The contents of the DAC registers are cleared, setting VOUT0 to VOUT39 to 0 V. The hardware reset activation time takes 270 µs.
AD5380 Data Sheet AD5380 INTERFACES Figure 3 and Figure 5 show timing diagrams for a serial write to the AD5380 in standalone and daisy-chain modes. The 24-bit data-word format for the serial interface is shown in Table 18. The AD5380 contains both parallel and serial interfaces. Furthermore, the serial interface can be programmed to be either SPI-, DSP-, MICROWIRE-, or I2C-compatible. The SER/PAR pin selects parallel and serial interface modes.
Data Sheet AD5380 Daisy-Chain Mode Readback Mode For systems that contain several devices, the SDO pin may be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. With R/W = 1, Bits A5 to A0, in association with Bits REG1 and REG0, select the register to be read.
AD5380 Data Sheet I2C SERIAL INTERFACE The AD5380 features an I2C-compatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the AD5380 and the master at rates up to 400 kHz. Figure 6 shows the 2-wire interface timing diagrams that incorporate three different modes of operation.
Data Sheet AD5380 SCL 1 SDA 0 1 0 1 AD1 AD0 START COND BY MASTER R/W 0 ACK BY AD538x MSB 0 A5 A4 A3 A2 A1 A0 ACK BY AD538x ADDRESS BYTE POINTER BYTE SCL REG1 REG0 MSB LSB MSB LSB ACK BY AD538x ACK BY AD538x MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE STOP COND BY MASTER 03731-031 SDA Figure 31.
AD5380 Data Sheet PARALLEL INTERFACE 2-Byte Mode The SER/PAR pin must be tied low to enable the parallel interface and disable the serial interfaces. Figure 7 shows the timing diagram for a parallel write. The parallel interface is controlled by the following pins: Following initialization of 2-byte mode, the user can update channels sequentially. The device address byte is only required once and the pointer address pointer is configured for autoincrement or burst mode.
Data Sheet AD5380 MICROPROCESSOR INTERFACING Parallel Interface The AD5380 can be interfaced to a variety of 16-bit microcontrollers or DSP processors. Figure 35 shows the AD5380 family interfaced to a generic 16-bit microcontroller/DSP processor. The lower address lines from the processor are connected to A0 to A5 on the AD5380. The upper address lines are decoded to provide a CS, LDAC signal for the AD5380.
AD5380 Data Sheet AD5380 to PIC16C6x/7x DVDD AD5380 SER/PAR SDO SDO/RC5 DIN SCK/RC3 SCLK RA1 SYNC SPI/I2C 03731-036 RESET SDI/RC4 Figure 36. AD5380-to-PIC16C6x/7x Interface RESET RxD SDO DIN TxD SCLK P1.1 03731-037 SYNC SPI/I2C Figure 37. AD5380-to-8051 Interface AD5380 to ADSP-2101/ADSP-2103 Figure 38 shows a serial interface between the AD5380 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set up to operate in SPORT transmit alternate framing mode.
Data Sheet AD5380 APPLICATION INFORMATION In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5380 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board.
AD5380 Data Sheet AD5380 MONITOR FUNCTION TOGGLE MODE FUNCTION The AD5380 contains a channel monitor function that consists of a multiplexer addressed via the interface, allowing any channel output to be routed to this pin for monitoring using an external ADC. In channel monitor mode, VOUT39 becomes the MON_OUT pin, to which all monitored signals are routed. The channel monitor function must be enabled in the control register before any channels are routed to MON_OUT.
Data Sheet AD5380 THERMAL MONITOR FUNCTION AD5380 IN A MEMS BASED OPTICAL SWITCH The AD5380 contains a temperature shutdown function to protect the chip in case multiple outputs are shorted. The shortcircuit current of each output amplifier is typically 40 mA. Operating the AD5380 at 5 V produces a power dissipation of 200 mW per shorted amplifier. With five channels shorted, this gives an extra watt of power dissipation. For the 100-lead LQFP, the θJA is typically 44°C/W.
AD5380 Data Sheet OPTICAL ATTENUATORS The AD5380 controls the optical attenuator for each wavelength, ensuring that the power is equalized in all wavelengths before being multiplexed onto the fiber. This prevents information loss and saturation from occurring at amplification stages further along the fiber.
Data Sheet AD5380 UTILIZING THE AD5380 FIFO In such systems, as many as 400 channels need to be updated within 40 µs. Four-hundred channels requires the use of 10 AD5380s. With FIFO mode enabled, the data write cycle time is 40 ns; therefore, each group consisting of 40 channels can be fully loaded in 1.6 µs. In FIFO mode, a complete group of 40 channels will update in 14.4 µs. The time taken to update all 400 channels is 14.4 µs + 9 × 1.6 µs = 28.8 µs. Figure 45 shows the FIFO operation scheme.
AD5380 Data Sheet OUTLINE DIMENSIONS 16.20 16.00 SQ 15.80 1.60 MAX 0.75 0.60 0.45 100 1 76 75 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY 51 50 25 26 VIEW A 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW 0.27 0.22 0.17 051706-A 1.45 1.40 1.35 COMPLIANT TO JEDEC STANDARDS MS-026-BED Figure 46.
Data Sheet AD5380 NOTES Rev.
AD5380 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03731-0-9/12(C) Rev.
