Datasheet

AD5379
Rev. B | Page 9 of 28
PARALLEL INTERFACE
V
CC
= 2.7 V to 5.5 V; V
DD
= 11.4 V to 16.5 V; V
SS
= −11.4 V to −16.5 V; AGND = DGND = DUTGND = 0 V; V
REF
(+) = 5 V;
V
REF
() = 3.5 V, FIFOEN = 0 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 5.
Parameter
1, 2, 3
Limit at T
MIN
to T
MAX
Unit Description
t
0
4.5 ns min
REG0, REG1, address to
WR
rising edge setup time.
t
1
4.5 ns min
REG0, REG1, address to
WR
rising edge hold time.
t
2
10 ns min
CS
pulse width low.
t
3
10 ns min
WR
pulse width low.
t
4
0 ns min
CS
to
WR
falling edge setup time.
t
5
0 ns min
WR
to
CS
rising edge hold time.
t
6
4.5 ns min
Data to
WR
rising edge setup time.
t
7
4.5 ns min
Data to
WR
rising edge hold time.
t
8
20 ns min
WR
pulse width high.
t
9
240 ns min
Minimum
WR
cycle time (single-channel write).
t
10
4
0/30 ns min/max
WR
rising edge to
BUSY
falling edge.
t
11
4
330 ns max
BUSY
pulse width low (single-channel update). See . Table 10
t
12
0 ns min
BUSY
rising edge to
WR
rising edge.
t
13
30 ns min
WR
rising edge to
LDAC
falling edge.
t
14
20 ns min
LDAC
pulse width low.
t
15
4
150 ns typ
BUSY
rising edge to DAC output response time.
t
16
20 ns min
LDAC
rising edge to
WR
rising edge.
t
17
0 ns min
BUSY
rising edge to
LDAC
falling edge.
t
18
100 ns typ
LDAC
falling edge to DAC output response time.
t
19
20/30 μs typ/ max DAC output settling time.
t
20
10 ns min
CLR
pulse width low.
t
21
350 ns max
CLR
/
RESET
pulse activation time.
t
22
10 ns min
RESET
pulse width low.
t
23
120 μs max
RESET
time indicated by
BUSY
low.
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with t
r
= t
f
= 2 ns (10% to 90% of V
CC
), and timed from a voltage level of 1.2 V.
3
See Figure 6.
4
Measured with load circuit shown in Figure 2.