Datasheet

AD5378
Rev. A | Page 25 of 28
ADDRESS DECODING
The AD5378 contains an 8-bit address bus, A7 to A0. This
address bus allows each DAC input register (x1), each offset (c)
register, and each gain (m) register to be individually updated.
The REG1 and REG0 bits in the special function register (SFR)
(see Table 10) show the decoding for data, offset, and gain
registers. When all 32 DAC channels are selected, Address
Bits A[3:0] are ignored.
Table 18. DAC Group Addressing
A7 A6 A5 A4 Group
0 0 0 0 All 32 DACs
0 0 0 1 Group A
0 0 1 0 Group B
0 0 1 1 Groups A, B
0 1 0 0 Group C
0 1 0 1 Groups A, C
0 1 1 0 Groups B, C
0 1 1 1 Groups A, B, C
1 0 0 0 Group D
1 0 0 1 Groups A, D
1 0 1 0 Groups B, D
1 0 1 1 Groups A, B, D
1 1 0 0 Groups C, D
1 1 0 1 Groups A, C, D
1 1 1 0 Groups B, C, D
1 1 1 1 Groups A, B, C, D
A3 A2 A1 A0 Data/Offset/Gain/INC-DEC Register
0 0 0 0 Register 0
0 0 0 1 Register 1
0 0 1 0 Register 2
0 0 1 1 Register 3
0 1 0 0 Register 4
0 1 0 1 Register 5
1 0 0 0 Register 6
1 0 0 1 Register 7