Datasheet

AD5378
Rev. A | Page 22 of 28
INTERFACES
The AD5378 contains parallel and serial interfaces. The active
interface is selected via the SER/
PAR
pin.
The AD5378 uses an internal FIFO memory to allow high
speed successive writes in both serial and parallel modes. The
user can continue writing new data to the AD5378 while write
instructions are being executed. The
BUSY
signal goes low
while instructions in the FIFO are being executed. Up to
120 successive instructions can be written to the FIFO at
maximum speed. When the FIFO is full, additional writes to the
AD5378 are ignored.
To minimize both the power consumption of the device and
on-chip digital noise, the active interface powers up fully only
when the device is being written to, that is, on the falling edge
of
WR
or on the falling edge of
SYNC
.
All digital interfaces are 2.5 V LVTTL-compatible when
operating from a 2.7 V to 3.6 V V
CC
supply.
PARALLEL INTERFACE
A pull-down on the SER/
PAR
pin makes the parallel interface
the default. If using the parallel interface, the SER/
PAR
pin can
be left unconnected. Figure 6 shows the timing diagram for a
parallel write to the AD5378. The parallel interface is controlled
by the following pins.
CS
Pin
Active low device select pin.
WR
Pin
On the rising edge of
WR
, with
CS
low, the address values at
Pins A7 to A0 are latched and data values at Pins DB13 to DB0
are loaded into the selected AD5378 input registers.
REG1, REG0 Pins
The REG1 and REG0 pins determine the destination register of
the data being written to the AD5378. See Table 12.
Table 12. Register Selection
REG1 REG0 Register Selected
1 1 Input Data Register (x1)
1 0 Offset Register (c)
0 1 Gain Register (m)
0 0 Special Function Register
DB13 to DB0 Pins
The AD5378 accepts a straight 14-bit parallel word on DB0 to
DB13, where DB13 is the MSB and DB0 is the LSB. See Table 13
to Table 17.
A7 to A0 Pins
Each of the 32 DAC channels can be addressed individually. In
addition, several channel groupings enable the user to simulta-
neously write the same data to multiple DAC channels. Address
Bits A7 to A4 are decoded to select one group or multiple
groups of registers. Address Bits A3 to A0 select one of ten
input data registers (x1), offset registers (c), or gain registers
(m). See Table 18.
SERIAL INTERFACE
The SER/
PAR
pin must be tied high to enable the serial inter-
face and disable the parallel interface. The serial interface is
controlled by the following pins.
SYNC
, DIN, SCLK
Standard 3-wire interface pins.
DCEN
Selects standalone mode or daisy-chain mode.
SDO
Data out pin for daisy-chain mode.
Figure 4 and Figure 5 show the timing diagrams for a serial
write to the AD5378 in standalone and daisy-chain modes,
respectively.
The 24-bit data-word format for the serial interface is shown in
Figure 21.
MSB
REG0 DB13–DB0
LSB
A7–A0 REG1
REGISTER DATA BITS
GROUP/CHANNEL
SELECT BITS
REGISTER SELECT
BITS
05292-021
Figure 21. Serial Data Format
Standalone Mode
By connecting the DCEN (daisy-chain enable) pin low,
standalone mode is enabled. The serial interface works with
both a continuous and a burst serial clock. The first falling edge
of
SYNC
starts the write cycle and resets a counter that counts
the number of serial clocks to ensure that the correct number of
bits is shifted into the serial shift register. Additional edges on
SYNC
are ignored until 24 bits are shifted in. Once 24 bits are
shifted in, the SCLK is ignored. For another serial transfer to
take place, the counter must be reset by the falling edge of
SYNC
.