Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- TABLE OF CONTENTS
- REVISION HISTORY
- GENERAL DESCRIPTION
- SPECIFICATIONS
- TIMING CHARACTERISTICS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- TERMINOLOGY
- FUNCTIONAL DESCRIPTION
- INTERFACES
- DATA DECODING
- ADDRESS DECODING
- POWER SUPPLY DECOUPLING
- TYPICAL APPLICATION CIRCUIT
- OUTLINE DIMENSIONS

AD5378
Rev. A | Page 12 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
123456789101112
123456789101112
A
B
C
D
E
F
G
H
J
K
L
M
A
B
C
D
E
F
G
H
J
K
L
M
AD5378
TOP VIEW
05292-007
Figure 7. Pin Configuration
Table 8. 108-Lead CSPBGA Ball Configuration
CSPBGA No. Ball Name
A1 REG0
A2 V
CC
3
A3 DB10
A4 AGND4
A5 V
BIAS
A6 VOUT5
A7 AGND3
A8 REFGNDA1
A9 V
DD
5
A10 V
SS
5
A11 V
SS
4
A12 V
DD
4
B1 REG1
B2 DGND4
B3 DB9
B4 CLR
B5 AGND
B6 AGND
B7 VOUT0
B8 VOUT1
B9 VOUT2
B10 VOUT25
B11 REFGNDD1
B12 VOUT24
C1 DB13
C2 DB12/SCLK
C3 DB11/DIN
CSPBGA No. Ball Name
C4
SER/
PAR
1
C5
LDAC
C6 VOUT6
C7 VOUT3
C8 VOUT4
C9 VOUT7
C10 VOUT28
C11 VOUT26
C12 VOUT27
D1 DB7
D2 DB8
D3 DGND1
D10 V
REF
1(−)
D11 VOUT29
D12 AGND
E1 DB5
E2 DB6
E3 V
CC
1
E10 REFGNDB2
E11 AGND
E12 VOUT30
F1 DB4
F2 DB3
F3 DB2
F10 V
DD
3
F11 REFGNDD2
F12 VOUT31
CSPBGA No. Ball Name
G1 DB1
G2 DB0
G3 BUSY
G10 V
SS
3
G11 VOUT23
G12 REFGNDC2
H1 WR
/DCEN
H2 SDO
3
H3 CS
/
SYNC
H10 VOUT22
H11 AGND
H12 AGND
J1 A0
J2 A1
J3 A2
J10 VOUT15
J11 VOUT20
J12 VOUT21
K1 A4
K2 A5
K3 A3
K4 DGND2
K5 REFGNDA2
K6 V
REF
2(−)
K7 VOUT10
K8 VOUT11
K9 AGND
CSPBGA No. Ball Name
K10 VOUT14
K11 VOUT18
K12 VOUT19
L1 A7
L2 A6
L3 N/C
2
L4 RESET
3
L5 AGND
L6 AGND2
L7 VOUT12
L8 VOUT8
L9 V
DD
1
L10 V
REF
2(+)
L11 VOUT16
L12 VOUT17
M1 DGND3
M2 V
CC
2
M3 FIFOEN
1
M4 AGND1
M5 VOUT13
M6 VOUT9
M7 REFGNDB1
M8 V
REF
1(+)
M9 V
SS
1
M10 V
SS
2
M11 V
DD
2
M12 REFGNDC1
_________________________
1
Internal 1 MΩ pull-down device on this logic input. Therefore, it can be left floating, and it defaults to a logic low condition.
2
N/C—Do not connect to this pin. Internal active pull-up device on these logic inputs. They default to a logic high condition.
3
Internal 1 MΩ pull-up device on this logic input. Therefore, it can be left floating, and it defaults to a logic high condition.