Datasheet

AD5378
Rev. A | Page 10 of 28
REG0,
REG1,
A7–A02
CS
WR
DB12–DB0
BUSY
LDAC
1
VOUT
1
LDAC
2
VOUT
2
CLR
VOUT
1
LDAC ACTIVE DURING BUSY.
2
LDAC ACTIVE AFTER BUSY.
RESET
VOUT
BUSY
t
0
t
1
t
4
t
5
t
2
t
3
t
9
t
8
t
6
t
7
t
16
t
10
t
11
t
13
t
14
t
12
t
15
t
19
t
14
t
18
t
20
t
21
t
22
t
21
t
23
t
19
t
17
05292-006
Figure 6. Parallel Interface Timing Diagram