32-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage Output DAC AD5378 FEATURES Interface options Parallel interface DSP/microcontroller-compatible 3-wire serial interface 2.5 V to 5.5 V JEDEC-compliant digital levels SDO daisy-chaining option Power-on reset Digital reset (RESET pin and soft reset function) 32-channel DAC in 13 mm × 13 mm 108-lead CSPBGA Guaranteed monotonic to 14 bits Buffered voltage outputs Output voltage span of 3.5 V × VREF(+) Maximum output voltage span of 17.
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AD5378 TABLE OF CONTENTS Features .............................................................................................. 1 Reference Selection .................................................................... 19 Applications ....................................................................................... 1 Calibration................................................................................... 20 Functional Block Diagram ...........................................................
AD5378 GENERAL DESCRIPTION The AD5378 contains 32 14-bit DACs in one CSPBGA package. The AD5378 provides a bipolar output range determined by the voltages applied to the VREF(+) and VREF(−) inputs. The maximum output voltage span is 17.5 V, corresponding to a bipolar output range of −8.75 V to +8.75 V, and is achieved with reference voltages of VREF(−) = −3.5 V and VREF(+) = +5 V. The AD5378 guarantees operation over a wide VSS/VDD supply range from ±11.4 V to ±16.5 V.
AD5378 SPECIFICATIONS VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; VREF(+) = +5 V; VREF(−) = −3.5 V; AGND = DGND = REFGND = 0 V; VBIAS = 5 V; CL = 200 pF to GND; RL = 11 kΩ to 3 V; gain = 1; offset = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
AD5378 Parameter POWER REQUIREMENTS VCC VDD VSS Power Supply Sensitivity2 ∆ Full Scale/∆ VDD ∆ Full Scale/∆ VSS ∆ Full Scale/∆ VCC ICC IDD ISS Power Dissipation Power Dissipation Unloaded (P) Power Dissipation Loaded (PTOTAL) Junction Temperature A Version1 Unit 2.7/5.5 8.5/16.5 −3/−16.5 V min/max V min/max V min/max −75 −75 −90 5 28 23 dB typ dB typ dB typ mA max mA max mA max VCC = 5.
AD5378 TIMING CHARACTERISTICS SERIAL INTERFACE VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; VREF(+) = +5 V; VREF(−) = −3.5 V; AGND = DGND = REFGND = 0 V; VBIAS = 5 V, FIFOEN = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter1, 2, 3 t1 t2 t3 t4 t54 t64 t7 t8 t9 t104, 5 t11 t124 t13 t14 t15 t16 t17 t18 t19 t206, 7 t217 t227 t237 t245 t25 t26 Limit at TMIN, TMAX 20 8 8 10 15 25 10 5 4.
AD5378 t1 SCLK 1 2 24 t3 t4 SYNC t7 24 t2 t5 t6 t8 t9 DB23 DIN DB0 t10 t11 BUSY t12 t13 t17 LDAC1 t14 VOUT1 t15 t13 LDAC2 t16 VOUT2 t17 t18 CLR t19 VOUT 1LDAC 2LDAC ACTIVE DURING BUSY. ACTIVE AFTER BUSY. t25 RESET BUSY t19 05292-004 VOUT t26 Figure 4. Serial Interface Timing Diagram (Standalone Mode) Rev.
AD5378 t1 SCLK 24 t3 t7 48 t22 t2 t21 t4 SYNC t8 DIN t9 D23 D0 D23' INPUT WORD FOR DAC N D0' INPUT WORD FOR DAC N+1 t20 SDO D23 UNDEFINED D0 INPUT WORD FOR DAC N t23 t13 LDAC t11 BUSY Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode) Rev.
AD5378 PARALLEL INTERFACE VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; AGND = DGND = DUTGND = 0 V; VREF(+) = +5 V; VREF(−) = −3.5 V, FIFOEN = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 6. Parameter1, 2, 3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t104 t114 t12 t13 t14 t154 t16 t17 t18 t19 t20 t21 t22 t23 Limit at TMIN to TMAX 4.5 4.5 10 10 0 0 4.5 4.
AD5378 t0 t1 REG0, REG1, A7–A02 t4 t5 t2 CS t9 t3 WR t8 t6 t16 t7 DB12–DB0 t12 t10 t11 BUSY t13 t14 t19 LDAC1 t15 VOUT1 t17 t14 LDAC2 t18 VOUT2 t19 t20 CLR t21 VOUT 1LDAC 2LDAC ACTIVE DURING BUSY. ACTIVE AFTER BUSY. t22 RESET t21 t23 BUSY Figure 6. Parallel Interface Timing Diagram Rev.
AD5378 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 7.
AD5378 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 A A B B C C D D F AD5378 F G TOP VIEW G H H J J K K L L M M 1 2 3 4 5 6 7 8 9 10 11 12 05292-007 E E Figure 7. Pin Configuration Table 8. 108-Lead CSPBGA Ball Configuration CSPBGA No.
AD5378 Table 9. Pin Function Descriptions Pin VCC(1–3) VSS(1–5) VDD(1–5) AGND(1–4) DGND(1–4) VREF1(+), VREF1(−) VREF2(+), VREF2(−) VBIAS VOUT0 to VOUT31 SER/PAR SYNC1 SCLK1 DIN1 SDO1 DCEN1 CS WR DB13 to DB0 A0 to A7 REG0 REG1 CLR BUSY LDAC Description Logic Power Supply. 2.7 V to 5.5 V. These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF tantalum capacitors. Negative Analog Power Supply. −11.4 V to −16.5 V for specified performance. These pins should be decoupled with 0.
AD5378 Pin FIFOEN RESET REFGNDA1 REFGNDA2 REFGNDB1 REFGNDB2 REFGNDC1 REFGNDC2 REFGNDD1 REFGNDD2 1 Description FIFO Enable. Level sensitive, active high. When connected to DVDD, the internal FIFO is enabled, allowing the user to write to the device at full speed. FIFO is available in both serial and parallel modes. The FIFOEN pin has an internal 1 MΩ pull-down resistor connected to ground, meaning that the FIFO is disabled by default. Asynchronous Digital Reset Input. Falling edge sensitive.
AD5378 TYPICAL PERFORMANCE CHARACTERISTICS 1.5 3 VDD = +12V VSS = –12V VREF(+) = +5V VREF(–) = –3.5V TMAX = 85°C 2 1.0 1 FS ERROR (mV) 0 0 –1 ZC –0.5 –2 VDD = +12V VSS = –12V VREF(+) = +5V VREF(–) = –3.5V TA = 25°C –3 –1.5 0 2 4 6 8 10 12 14 16 AD5378 CODE (103) –4 –40 05292-008 –1.0 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 8. Typical INL Plot 05292-011 INL (LSBs) 0.5 Figure 11. Typical Full-Scale and Zero-Scale Errors vs. Temperature 1400 19.
AD5378 3.5 VDD = +12V VSS = –12V VREF(+) = +5V VREF(–) = –3.5V 3.0 TA = 25°C VDD = +12V VSS = –12V VREF(+) = +5V VREF(–) = –3.5V VOUT ICC (mA) 2.5 2.0 1.5 +85°C 1.0 –40°C 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 10V Figure 14. ICC vs. Supply Figure 17. DAC-to-DAC Crosstalk –0.208 1.75 TA = 25°C VDD = +12V VSS = –12V VREF(+) = +5V VREF(–) = –3.5V –0.211 TA = 25°C VDD = +12V VSS = –12V VREF(+) = +5V VREF(–) = –3.5V VCC = +3.3V 1.70 1.65 1.60 –0.
AD5378 TERMINOLOGY Relative Accuracy Relative accuracy or endpoint linearity is a measurement of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error and is expressed in least significant bits (LSB). Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
AD5378 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL The AD5378 contains 32 DAC channels and 32 output amplifiers in a single package. The architecture of a single DAC channel consists of a 14-bit resistor-string DAC followed by an output buffer amplifier. The resistor-string section is simply a string of resistors, each of value R, from VREF(+) to AGND. This type of architecture guarantees DAC monotonicity.
AD5378 VBIAS FUNCTION The AD5378 on-chip voltage generator provides a bias voltage of 4.25 V (min). The VBIAS pin is provided for bypassing and overdriving purposes only. It is not intended to be used as a supply or a reference. If VREF(+) > 4.25 V, VBIAS must be pulled high externally to an equal or higher potential such as 5 V. The external voltage source should be capable of driving a 50 μA (typical) current sink load.
AD5378 CALIBRATION Software Clear The user can perform a system calibration by overwriting the default values in the m and c registers for any individual DAC channel as follows: Loading a clear code to the x1 registers also enables the user to set VOUT0 to VOUT31 to the REFGND level. The default clear code corresponds to m at full scale and c at midscale (x2 = x1). 1. Calculate the nominal offset and gain coefficients for the new output range (see the revious example). 2.
AD5378 FIFO VS. NON-FIFO OPERATION Data can be loaded to the AD5378 registers with FIFO disabled or enabled. Operation with FIFO disabled is optimum for single writes to the device. If the system requires significant data transfers to the AD5378, however, operation with FIFO enabled is more efficient. When FIFO is enabled, the AD5378 uses an internal FIFO memory to allow high speed successive writes in both serial and parallel modes.
AD5378 INTERFACES The AD5378 contains parallel and serial interfaces. The active interface is selected via the SER/PAR pin. The AD5378 uses an internal FIFO memory to allow high speed successive writes in both serial and parallel modes. The user can continue writing new data to the AD5378 while write instructions are being executed. The BUSY signal goes low while instructions in the FIFO are being executed. Up to 120 successive instructions can be written to the FIFO at maximum speed.
AD5378 Daisy-Chain Mode For systems that contain several DACs, the SDO pin can be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. Connecting the DCEN (daisy-chain enable) pin high enables daisy-chain mode. The first falling edge of SYNC starts the write cycle. The SCLK is continuously applied to the input shift register when SYNC is low.
AD5378 DATA DECODING The AD5378 contains a 14-bit data bus, DB13 to DB0. Depending on the value of REG1 and REG0, this data is loaded into the addressed DAC input register(s), offset (c) register(s), gain (m) register(s), or the special function register. Table 13.
AD5378 ADDRESS DECODING The AD5378 contains an 8-bit address bus, A7 to A0. This address bus allows each DAC input register (x1), each offset (c) register, and each gain (m) register to be individually updated. The REG1 and REG0 bits in the special function register (SFR) (see Table 10) show the decoding for data, offset, and gain registers. When all 32 DAC channels are selected, Address Bits A[3:0] are ignored. Table 18.
AD5378 POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5378 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5378 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only.
AD5378 TYPICAL APPLICATION CIRCUIT The high channel count of the AD5378 makes it wellsuited to applications requiring high levels of integration such as optical and automatic test equipment (ATE) systems. Figure 22 shows the AD5378 as it is used in an ATE system. Shown here is one pin of a typical logic tester. It is apparent that a number of discrete levels are required for the pin driver, active load circuit, parametric measurement unit, comparators, and clamps.
AD5378 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 13.00 BSC SQ 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M BALL A1 INDICATOR 11.00 BSC SQ TOP VIEW BOTTOM VIEW 1.00 BSC *1.85 1.70 1.55 DETAIL A DETAIL A 1.05 1.00 0.90 0.75 0.70 0.65 SEATING PLANE *0.64 TYP 0.12 MAX COPLANARITY *COMPLIANT WITH JEDEC STANDARDS MO-192-AAD-1 WITH THE EXCEPTION OF PACKAGE HEIGHT AND BALL DIAMETER. 012006-0 BALL DIAMETER Figure 23.
