Datasheet

AD5372/AD5373
Rev. C | Page 7 of 28
SCLK
SYNC
SDI
BUSY
V
OUTx
1
V
OUTx
2
VOUTx
RESET
VOUTx
CLR
1
2
24
t
8
t
12
t
10
t
13
t
17
t
14
t
15
t
13
t
17
t
9
t
7
t
5
t
4
t
2
t
6
DB23
DB0
t
16
1
LDAC ACTIVE DURING BUSY.
2
LDAC ACTIVE AFTER BUSY.
BUSY
LDAC
1
LDAC
2
1
t
3
t
20
t
23
t
18
t
18
t
19
24
t
11
t
1
05815-004
Figure 4. SPI Write Timing