Datasheet

AD5372/AD5373
Rev. C | Page 3 of 28
GENERAL DESCRIPTION
The AD5372/AD5373 contain 32 16-/14-bit DACs in 64-lead
LQFP and LFCSP packages. The devices provide buffered
voltage outputs with a nominal span of 4× the reference voltage.
The gain and offset of each DAC can be independently trimmed
to remove errors. For even greater flexibility, the device is divided
into four groups of eight DACs. Two offset DACs allow the
output range of the groups to be altered. Group 0 can be adjusted
by Offset DAC 0, and Group 1 to Group 3 can be adjusted by
Offset DAC 1.
The AD5372/AD5373 offer guaranteed operation over a wide
supply range: V
SS
from −16.5 V to −4.5 V and V
DD
from 9 V to
16.5 V. The output amplifier headroom requirement is 1.4 V
operating with a load current of 1 mA.
The AD5372/AD5373 have a high speed serial interface that is
compatible with SPI, QSPI™, MICROWIRE™, and DSP inter-
face standards and can handle clock speeds of up to 50 MHz.
The DAC registers are updated on reception of new data. All
the outputs can be updated simultaneously by taking the
LDAC
input low. Each channel has a programmable gain and an offset
adjust register.
Each DAC output is gained and buffered on chip with respect
to an external SIGGNDx input. The DAC outputs can also be
switched to SIGGNDx via the
CLR
pin.
Table 1. High Channel Count Bipolar DACs
Model Resolution (Bits) Nominal Output Span Output Channels Linearity Error (LSB)
AD5360 16 4 × V
REF
(20 V) 16 ±4
AD5361 14 4 × V
REF
(20 V) 16 ±1
AD5362 16 4 × V
REF
(20 V) 8 ±4
AD5363 14 4 × V
REF
(20 V) 8 ±1
AD5370 16 4 × V
REF
(12 V) 40 ±4
AD5371 14 4 × V
REF
(12 V) 40 ±1
AD5372 16 4 × V
REF
(12 V) 32 ±4
AD5373 14 4 × V
REF
(12 V) 32 ±1
AD5378 14 ±8.75 V 32 ±3
AD5379 14 ±8.75 V 40 ±3