32-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC AD5372/AD5373 FEATURES 2.5 V to 5.
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AD5372/AD5373 TABLE OF CONTENTS Features .............................................................................................. 1 Reference Selection .................................................................... 17 Applications....................................................................................... 1 Calibration................................................................................... 18 Functional Block Diagram .....................................................
AD5372/AD5373 GENERAL DESCRIPTION The AD5372/AD5373 contain 32 16-/14-bit DACs in 64-lead LQFP and LFCSP packages. The devices provide buffered voltage outputs with a nominal span of 4× the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility, the device is divided into four groups of eight DACs. Two offset DACs allow the output range of the groups to be altered.
AD5372/AD5373 SPECIFICATIONS DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = open circuit; RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
AD5372/AD5373 Parameter POWER REQUIREMENTS DVCC VDD VSS Power Supply Sensitivity2 ∆Full Scale/∆VDD ∆Full Scale/∆VSS ∆Full Scale/∆DVCC DICC IDD ISS Power-Down Mode DICC IDD ISS Power Dissipation (Unloaded) Junction Temperature 3 AD5372 1 B Version AD53731 B Version Unit 2.5/5.5 9/16.5 −16.5/−4.5 2.5/5.5 9/16.5 −16.5/−4.
AD5372/AD5373 TIMING CHARACTERISTICS DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; VREFx = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pF to GND; RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted. Table 4. SPI Interface Parameter 1, 2, 3 t1 t2 t3 t4 t5 t6 t7 t8 t9 4 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 5 t23 Limit at TMIN, TMAX 20 8 8 11 20 10 5 5 42 1/1.
AD5372/AD5373 t1 SCLK 1 24 2 t3 t4 SYNC 24 t11 t6 t5 t7 SDI 1 t2 t8 DB0 DB23 t9 t10 BUSY t12 t13 LDAC1 t17 t14 VOUTx1 t15 t13 LDAC2 t17 VOUTx2 t16 CLR t18 VOUTx t19 RESET VOUTx t18 t20 BUSY 05815-004 t23 1 LDAC ACTIVE DURING BUSY. 2 LDAC ACTIVE AFTER BUSY. Figure 4. SPI Write Timing Rev.
AD5372/AD5373 t22 SCLK 48 t21 SYNC DB23 DB0 DB23 INPUT WORD SPECIFIES REGISTER TO BE READ DB0 NOP CONDITION DB0 SDO DB23 DB15 SELECTED REGISTER DATA CLOCKED OUT LSB FROM PREVIOUS WRITE Figure 5. SPI Read Timing OUTPUT VOLTAGE FULL-SCALE ERROR + ZERO-SCALE ERROR 8V ACTUAL TRANSFER FUNCTION IDEAL TRANSFER FUNCTION –4V DAC CODE 16383 ZERO-SCALE ERROR 05815-006 0 Figure 6. DAC Transfer Function Rev.
AD5372/AD5373 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 60 mA do not cause SCR latch-up. Table 5.
AD5372/AD5373 RESET BUSY VOUT27 SIGGND3 VOUT28 VOUT29 VOUT30 VOUT31 NC NC NC NC NC NC NC VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD5372/AD5373 TOP VIEW (Not to Scale) VOUT6 VOUT7 DGND DVCC SYNC SCLK SDI SDO DVCC DGND AGND VOUT24 VOUT25 VOUT26 LDAC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PIN 1 INDICATOR CLR CLR LDAC VOUT26 VOUT25 VOUT24 AGND DGND DVCC SDO SDI SCLK SYNC DVCC DGND
AD5372/AD5373 Pin No. 56 Mnemonic SDO 59 63 AGND LDAC 64 CLR Description Serial Data Output. CMOS output. SDO can be used for readback. Data is clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK. Ground for All Analog Circuitry. The AGND pin should be connected to the AGND plane. Load DAC Logic Input (Active Low). See the BUSY and LDAC Functions section for more information. Asynchronous Clear Input (Level Sensitive, Active Low).
AD5372/AD5373 TYPICAL PERFORMANCE CHARACTERISTICS 0.0050 2 TA = 25°C VSS = –15V VDD = +15V VREFx = +4.096V 0.0025 AMPLITUDE (V) 0 –0.0025 05815-008 –1 –2 0 0 16384 32768 49152 –0.0050 65535 05815-011 INL (LSB) 1 0 1 2 DAC CODE Figure 9. Typical AD5372 INL Plot 1.0 VDD = +15V VSS = –15V DVCC = +5V VREFx = +3V 0.5 DNL (LSB) 0 0 –0.5 05815-009 –0.5 0 20 40 –1.0 80 60 05815-012 INL ERROR (LSB) 0.5 0 16384 49152 65535 Figure 13. Typical AD5372 DNL Plot Figure 10.
AD5372/AD5373 0.50 12 NUMBER OF UNITS DICC (mA) 0.45 DVCC = +5.5V 0.40 VSS = –15V VDD = +15V TA = 25°C 14 VSS = –12V VDD = +12V VREFx = +3V DVCC = +3.6V 0.35 DVCC = +2.5V 10 8 6 4 0.30 –20 0 20 40 60 0 80 05815-016 05815-014 0.25 –40 2 12.6 12.8 TEMPERATURE (°C) 13.2 13.4 Figure 17. Typical IDD Distribution Figure 15. DICC vs. Temperature 13.5 14 IDD DVCC = 5V TA = 25°C 12 NUMBER OF UNITS 13.0 12.5 ISS 10 8 6 4 VSS = –12V VDD = +12V VREFx = +3V 11.
AD5372/AD5373 TERMINOLOGY Integral Nonlinearity (INL) Integral nonlinearity, or endpoint linearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error and is expressed in least significant bits (LSB). Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
AD5372/AD5373 THEORY OF OPERATION DAC ARCHITECTURE The AD5372/AD5373 contain 32 DAC channels and 32 output amplifiers in a single package. The architecture of a single DAC channel consists of a 16-bit (AD5372) or 14-bit (AD5373) resistor-string DAC followed by an output buffer amplifier. The resistor-string section is simply a string of resistors (of equal value) from VREF0 or VREF1 to AGND. This type of architecture guarantees DAC monotonicity.
AD5372/AD5373 A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT LOAD DAC Each DAC channel has seven data registers. The actual DAC data-word can be written to either the X1A or the X1B input register, depending on the setting of the A/B bit in the control register. If the A/B bit is 0, data is written to the X1A register. If the A/B bit is 1, data is written to the X1B register. Note that this single bit is a global control and affects every DAC channel in the device.
AD5372/AD5373 OUTPUT AMPLIFIER Because the output amplifiers can swing to 1.4 V below the positive supply and 1.4 V above the negative supply, this limits how much the output can be offset for a given reference voltage. For example, it is not possible to have a unipolar output range of 20 V, because the maximum supply voltage is ±16.5 V.
AD5372/AD5373 The required reference levels can be calculated as follows: CALIBRATION 1. 2. Identify the nominal output range on VOUT. Identify the maximum offset span and the maximum gain required on the full output signal range. Calculate the new maximum output range on VOUT, including the expected maximum offset and gain errors. Choose the new required VOUTMAX and VOUTMIN, keeping the VOUT limits centered on the nominal values. Note that VDD and VSS must provide sufficient headroom.
AD5372/AD5373 ADDITIONAL CALIBRATION BUSY AND LDAC FUNCTIONS The techniques described in the previous section are usually enough to reduce the zero-scale and full-scale errors in most applications. However, there are limitations whereby the errors may not be sufficiently reduced. For example, the offset (C) register can only be used to reduce the offset caused by the negative zero-scale error. A positive offset cannot be reduced.
AD5372/AD5373 POWER-DOWN MODE TOGGLE MODE The AD5372/AD5373 can be powered down by setting Bit 0 in the control register to 1. This turns off the DACs, thus reducing the current consumption. The DAC outputs are connected to their respective SIGGNDx potentials. The power-down mode does not change the contents of the registers, and the DACs return to their previous voltage when the power-down bit is cleared to 0.
AD5372/AD5373 SERIAL INTERFACE The AD5372/AD5373 contain a high speed SPI operating at clock frequencies up to 50 MHz (20 MHz for read operations). To minimize both the power consumption of the device and on-chip digital noise, the interface powers up fully only when the device is being written to, that is, on the falling edge of SYNC. The serial interface is 2.5 V LVTTL-compatible when operating from a 2.5 V to 3.6 V DVCC supply.
AD5372/AD5373 CHANNEL ADDRESSING AND SPECIAL MODES If the mode bits are not 00, the data-word D15 to D0 (AD5372) or D13 to D0 (AD5373) is written to the device. Address Bit A5 to Address Bit A0 determine which channels are written to, and the mode bits determine to which register (X1A, X1B, C, or M) the data is written, as shown in Table 13 and Table 14. Data is to be written to the X1A register when the A/B bit in the control register is 0, or to the X1B register when the A/B bit is 1. Table 13.
AD5372/AD5373 SPECIAL FUNCTION MODE If the mode bits are 00, then the special function mode is selected, as shown in Table 15. Bit I21 to Bit I16 of the serial data-word select the special function, and the remaining bits are data required for execution of the special function, for example, the channel address for data readback. The codes for the special functions are shown in Table 16. Table 17 shows the addresses for data readback. Table 15.
AD5372/AD5373 APPLICATIONS INFORMATION INTERFACING EXAMPLES The SPI interface of the AD5372/AD5373 is designed to allow the parts to be easily connected to industry-standard DSPs and microcontrollers. Figure 22 shows how the AD5372/AD5373 connects to the Analog Devices, Inc., Blackfin® DSP.
AD5372/AD5373 OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 64 1 49 PIN 1 INDICATOR 48 PIN 1 INDICATOR 0.50 BSC 8.75 BSC SQ (BOTTOM VIEW) 0.50 0.40 0.30 16 17 33 32 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 12° MAX FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM 0.30 0.23 0.18 SEATING PLANE 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 24.
AD5372/AD5373 ORDERING GUIDE Model 1 AD5372BSTZ AD5372BSTZ-REEL AD5372BCPZ AD5372BCPZ-RL7 AD5373BSTZ AD5373BSTZ-REEL AD5373BCPZ AD5373BCPZ-RL7 EVAL-AD5372EBZ EVAL-AD5373EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 64-Lead Low Profile Quad Flat Package (LQFP) 64-Lead Low Profile Quad Flat Package (LQFP) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package
AD5372/AD5373 NOTES Rev.
AD5372/AD5373 NOTES ©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05815-0-7/11(C) Rev.
