Datasheet

AD5370
Rev. 0 | Page 4 of 28
SPECIFICATIONS
PERFORMANCE SPECIFICATIONS
DV
CC
= 2.5 V to 5.5 V; V
DD
= 9 V to 16.5 V; V
SS
= −16.5 V to −8 V; V
REF
= 3 V; AGND = DGND = SIGGND = 0 V; C
L
= open circuit;
R
L
= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter Min Type Max Unit Test Conditions/Comments
1
ACCURACY
Resolution 16 Bits
Integral Nonlinearity −4 +4 LSB
Differential Nonlinearity −1 +1 LSB Guaranteed monotonic by design
Zero-Scale Error −10 +10 mV Before calibration
Full-Scale Error −10 +10 mV Before calibration
Gain Error 0.1 % FSR
Zero-Scale Error
2
1 LSB After calibration
Full-Scale Error
2
1 LSB After calibration
Span Error of Offset DAC −35 +35 mV
See the
Offset DAC Channels section for
details
VOUT Temperature Coefficient
(VOUT0 to VOUT39)
5 ppm FSR/°C Includes linearity, offset, and gain drift
DC Crosstalk
2
120 µV
Typically 20 µV; measured channel at midscale,
full-scale change on any other channel
REFERENCE INPUTS (VREF0, VREF1)
2
VREF Input Current −10 +10 µA Per input, typically ±30 nA
VREF Range 2 5 V ±2% for specified operation
SIGGND INPUT (SIGGND0 to SIGGND4)
2
DC Input Impedance 50 kΩ Typically 55 kΩ
Input Range −0.5 +0.5 V
SIGGND Gain 0.995 1.005
OUTPUT CHARACTERISTICS
2
Output Voltage Range V
SS
+ 1.4 V
DD
− 1.4 V I
LOAD
= 1 mA
Nominal Output Voltage Range −4 +8 V
Short-Circuit Current 15 mA VOUTx to DV
CC
, V
DD
, or V
SS
Load Current −1 +1 mA
Capacitive Load 2200 pF
DC Output Impedance 0.5
DIGITAL INPUTS
Input High Voltage 1.7 V DV
CC
= 2.5 V to 3.6 V
2.0 V DV
CC
= 3.6 V to 5.5 V
Input Low Voltage 0.8 V DV
CC
= 2.5 V to 5.5 V
Input Current −1 +1 µA
Excluding the
CLR pin
CLR High Impedance Leakage
Current
−20 +20 µA
Input Capacitance
2
10 pF
DIGITAL OUTPUTS (SDO, BUSY)
Output Low Voltage 0.5 V Sinking 200 A
Output High Voltage (SDO) DV
CC
− 0.5 V Sourcing 200 A
SDO High Impedance Leakage
Current
−5 +5 µA
High Impedance Output
Capacitance
2
10 pF