Datasheet

AD5370
Rev. 0 | Page 11 of 28
Pin No. Mnemonic Description
16, 35 V
DD
Positive Analog Power Supply; +9 V to +16.5 V for specified performance. These pins
should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors.
17, 36 V
SS
Negative Analog Power Supply; −16.5 V to −8 V for specified performance. These pins
should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors.
51, 58 DGND Ground for All Digital Circuitry. Both DGND pins should be connected to the DGND plane.
52, 57 DV
CC
Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 µF ceramic
capacitors and 10 µF capacitors.
53
SYNC Active Low Input. This is the frame synchronization signal for the serial interface. See the
Timing Characteristics section for more details.
54 SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This
pin operates at clock speeds up to 50 MHz. See the
Timing Characteristics section for
more details.
55 SDI
Serial Data Input. Data must be valid on the falling edge of SCLK. See the
Timing
Characteristics
section for more details.
56 SDO
Serial Data Output for SPI Interface. CMOS output. SDO can be used for readback. Data is
clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK.
59 AGND Ground for All Analog Circuitry. The AGND pin should be connected to the AGND plane.
63
LDAC
Load DAC Logic Input (Active Low).
64
CLR Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear Function section for
more information.
Exposed Paddle
The lead-free chip scale package (LFCSP) has an exposed paddle on the underside. The
paddle should be connected to V
SS
.