40-Channel,16-Bit, Serial Input, Voltage Output DAC AD5370 FEATURES 2.5 V to 5.
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AD5370 TABLE OF CONTENTS Features .............................................................................................. 1 Transfer Function....................................................................... 17 Applications....................................................................................... 1 Reference Selection .................................................................... 17 Functional Block Diagram ..............................................................
AD5370 GENERAL DESCRIPTION The AD5370 1 contains forty 16-bit DACs in a single 64-lead LFCSP and a 64-lead LQFP. The device provides buffered voltage outputs with a span that is 4× the reference voltage. The gain and offset of each DAC channel can be independently trimmed to remove errors. For even greater flexibility, the device is divided into five groups of eight DACs. Three offset DAC channels allow the output range of blocks to be adjusted.
AD5370 SPECIFICATIONS PERFORMANCE SPECIFICATIONS DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; CL = open circuit; RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
AD5370 Parameter POWER REQUIREMENTS DVCC VDD VSS Power Supply Sensitivity2 ∆Full Scale/∆VDD ∆Full Scale/∆VSS ∆Full Scale/∆DVCC DICC Min Type 2.5 9 −16.5 Power Dissipation Unloaded (P) Power-Down Mode DICC IDD ISS Junction Temperature 3 3 5.5 16.5 −4.5 V V V 2 dB dB dB mA 18 20 −18 −20 ISS 2 Unit −75 −75 −90 IDD 1 Max 280 5 35 −35 mA mA mA mA mW μA μA μA °C 130 Test Conditions/Comments 1 DVCC = 5.
AD5370 TIMING CHARACTERISTICS DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −4.5 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF to GND; RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted. Table 4. SPI Interface Parameter 1, 2, 3 t1 t2 t3 t4 t5 t6 t7 t8 t94 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t225 t23 Limit at TMIN, TMAX Min Typ Max 20 8 8 11 20 10 5 5 42 1.
AD5370 t1 SCLK 1 24 2 t3 t4 SYNC 24 t11 t6 t5 t7 SDI 1 t2 t8 DB0 DB23 t9 t10 BUSY t12 t13 LDAC1 t17 t14 VOUTx1 t15 t13 LDAC2 t17 VOUTx2 t16 CLR t18 VOUTx t19 RESET VOUTx t18 t20 BUSY 05813-004 t23 1 LDAC ACTIVE DURING BUSY. 2 LDAC ACTIVE AFTER BUSY. Figure 4. SPI Write Timing Rev.
AD5370 t22 SCLK 48 t21 SYNC DB23 DB0 DB23 INPUT WORD SPECIFIES REGISTER TO BE READ DB0 NOP CONDITION DB0 SDO DB23 SELECTED REGISTER DATA CLOCKED OUT LSB FROM PREVIOUS WRITE Figure 5. SPI Read Timing Rev.
AD5370 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 60 mA do not cause SCR latch-up. Table 5.
AD5370 VOUT24 VOUT25 TOP VIEW (Not to Scale) VOUT6 VOUT7 DGND DVCC SYNC SCLK SDI SDO DVCC DGND 47 VOUT4 46 SIGGND0 VOUT27 3 SIGGND3 4 45 VOUT3 VOUT28 5 44 VOUT2 VOUT29 6 43 VOUT1 AD5370 VOUT30 7 42 VOUT0 TOP VIEW (Not to Scale) VOUT31 8 41 VREF0 VOUT32 9 40 VOUT23 VOUT33 10 39 VOUT22 VOUT34 11 38 VOUT21 VOUT35 12 37 VOUT20 SIGGND4 13 36 VSS VOUT36 14 35 VDD VOUT37 15 34 SIGGND2 Figure 6.
AD5370 Pin No. 16, 35 Mnemonic VDD 17, 36 VSS 51, 58 52, 57 DGND DVCC 53 SYNC 54 SCLK 55 SDI 56 SDO 59 63 64 AGND LDAC CLR Exposed Paddle Description Positive Analog Power Supply; +9 V to +16.5 V for specified performance. These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. Negative Analog Power Supply; −16.5 V to −8 V for specified performance. These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
AD5370 TYPICAL PERFORMANCE CHARACTERISTICS 2 0 TA = 25°C VSS = –15V VDD = +15V VREF = +4.096V AMPLITUDE (V) INL (LSB) 1 0 –0.01 16384 0 32768 49152 –0.02 05813-009 –2 65535 DAC CODE 0 2 4 6 8 10 TIME (µs) Figure 8.Typical INL Plot 05813-012 –1 Figure 11. Analog Crosstalk Due to LDAC 7 0.0050 VDD = +15V VSS = –15V TA = 25°C 6 TA = 25°C VSS = –15V VDD = +15V VREF = +4.096V AMPLITUDE (V) NUMBER OF UNITS 0.0025 5 4 3 2 0 –0.0025 –0.6 –0.3 0 0.3 –0.
600 14 500 12 NUMBER OF UNITS 400 300 200 10 8 6 4 2 100 0 1 2 3 FREQUENCY (Hz) 4 5 05813-015 0 0 VDD = 15V VSS = 15V TA = 25°C 13.00 Figure 14. Noise Spectral Density 0.50 13.75 14 14.00 DVCC = 5V TA = 25°C 12 NUMBER OF UNITS 0.45 DICC (mA) 13.50 IDD (mA) Figure 17. Typical IDD Distribution VSS = –12V VDD = +12V VREF = +3V DVCC = +5.5V 0.40 13.25 05813-018 OUTPUT NOISE (nV/ Hz) AD5370 DVCC = +3.6V 0.35 DVCC = +2.5V 10 8 6 4 0.
AD5370 TERMINOLOGY Integral Nonlinearity (INL) Integral nonlinearity, or endpoint linearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error and is expressed in least significant bits (LSB). Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
AD5370 THEORY OF OPERATION DAC ARCHITECTURE CHANNEL GROUPS The AD5370 contains 40 DAC channels and 40 output amplifiers in a single package. The architecture of a single DAC channel consists of a 16-bit resistor-string DAC followed by an output buffer amplifier. The resistor-string section is simply a string of resistors, of equal value, from VREF to AGND. This type of architecture guarantees DAC monotonicity.
AD5370 A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT LOAD DAC Each DAC channel has seven data registers. The actual DAC data-word can be written to either the X1A or X1B input register, depending on the setting of the A/B bit in the Control register. If the A/B bit is 0, data is written to the X1A register. If the A/B bit is 1, data is written to the X1B register. Note that this single bit is a global control and affects every DAC channel in the device.
AD5370 OUTPUT AMPLIFIER The output amplifiers can swing to 1.4 V below the positive supply and 1.4 V above the negative supply, which limits how much the output can be offset for a given reference voltage. For example, it is not possible to have a unipolar output range of 20 V because the maximum supply voltage is ±16.5 V.
AD5370 Reference Selection Example Reducing Full-scale Error If Full-scale error can be reduced as follows: • • • • 1. 2. 3. Nominal Output Range = 12 V (−4 V to +8 V) Zero-Scale Error = ±70 mV Gain Error = ±3% SIGGND = AGND = 0 V Then • • • 4. Gain Error = ±3% => Maximum Positive Gain Error = +3% => Output Range Including Gain Error = 12 + 0.03(12) = 12.36 V Offset Error = ±70 mV => Maximum Offset Error Span = 2(70 mV) = 0.14 V => Output Range Including Gain Error and Offset Error = 12.36 V + 0.
AD5370 RESET FUNCTION The reset function is initiated by the RESET pin. On the rising edge of RESET, the AD5370 state machine initiates a reset sequence to reset the X, M, and C registers to their default values. This sequence typically takes 300 μs, and the user should not write to the part during this time. On power-up, it is recommended that the user bring RESET high as soon as possible to properly initialize the registers.
AD5370 TOGGLE MODE The AD5370 has two X2 registers per channel, X2A and X2B, that can be used to switch the DAC output between two levels with ease. This approach greatly reduces the overhead required by a microprocessor that would otherwise have to write to each channel individually. When the user writes to the X1A, X2A, M, or C register, the calculation engine takes a certain amount of time to calculate the appropriate X2A or X2B value.
AD5370 SERIAL INTERFACE The AD5370 contains a high speed SPI-compatible serial interface operating at clock frequencies up to 50 MHz (20 MHz for read operations). To minimize both the power consumption of the device and on-chip digital noise, the interface powers up fully only when the device is being written to, that is, on the falling edge of SYNC. The serial interface is 2.5 V LVTTL-compatible when operating from a 2.5 V to 3.6 V DVCC supply.
AD5370 Table 11 shows the groups and channels that are addressed for every combination of Address Bit A5 to Address Bit A0. Table 11.
AD5370 SPECIAL FUNCTION MODE If the mode bits are 00, the special function mode is selected, as shown in Table 12. Bit I21 to Bit I16 of the serial data-word select the special function, and the remaining bits are data required for execution of the special function, for example, the channel address for data readback. The codes for the special functions are shown in Table 13. Table 14 shows the addresses for data readback. Table 12.
AD5370 Table 14.
AD5370 POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5370 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5370 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only.
AD5370 The SPI interface of the AD5370 is designed to allow the parts to be easily connected to industry-standard DSPs and microcontrollers. Figure 23 shows how the AD5370 can be connected to the Analog Devices, Inc., Blackfin® DSP. The Blackfin has an integrated SPI port that can be connected directly to the SPI pins of the AD5370, as well as programmable input/output pins that can be used to set or read the state of the digital input or output pins associated with the interface.
AD5370 OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 64 1 49 48 PIN 1 INDICATOR PIN 1 INDICATOR 0.50 BSC 8.75 BSC SQ TOP VIEW 0.50 0.40 0.30 16 17 33 32 0.80 MAX 0.65 TYP 12° MAX 0.25 MIN 7.50 REF 0.05 MAX 0.02 NOM 0.30 0.23 0.18 SEATING PLANE 0.20 REF 051007-C 1.00 0.85 0.80 7.25 7.10 SQ 6.95 EXPOSED PAD (BOTTOM VIEW) COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 25.
AD5370 NOTES © 2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05813-0-4/08(0) Rev.