Datasheet

AD5362/AD5363
Rev. A | Page 3 of 28
GENERAL DESCRIPTION
The AD5362/AD5363 contain eight 16-/14-bit DACs in a single
52-lead LQFP package or 56-lead LFCSP package. The devices
provide buffered voltage outputs with a span of 4× the reference
voltage. The gain and offset of each DAC can be independently
trimmed to remove errors. For even greater flexibility, the device
is divided into two groups of four DACs, and the output range
of each group can be independently adjusted by an offset DAC.
The AD5362/AD5363 offer guaranteed operation over a wide
supply range with V
SS
from −16.5 V to −4.5 V and V
DD
from 8 V
to 16.5 V. The output amplifier headroom requirement is 1.4 V,
operating with a load current of 1 mA.
The AD5362/AD5363 have a high speed 4-wire serial interface
that is compatible with SPI, QSPI™, MICROWIRE™, and DSP
interface standards and can handle clock speeds of up to
50 MHz. All the outputs can be updated simultaneously by
taking the
LDAC
input low. Each channel has a programmable
gain and an offset adjust register.
Each DAC output is gained and buffered on chip with respect
to an external SIGGNDx input. The DAC outputs can also be
switched to SIGGNDx via the
CLR
pin.
Table 1. High Channel Count Bipolar DACs
Model Resolution (Bits) Nominal Output Span Output Channels Linearity Error (LSB)
AD5360 16 4 × V
REF
(20 V) 16 ±4
AD5361 14 4 × V
REF
(20 V) 16 ±1
AD5362 16 4 × V
REF
(20 V) 8 ±4
AD5363 14 4 × V
REF
(20 V) 8 ±1
AD5370 16 4 × V
REF
(12 V) 40 ±4
AD5371 14 4 × V
REF
(12 V) 40 ±1
AD5372 16 4 × V
REF
(12 V) 32 ±4
AD5373 14 4 × V
REF
(12 V) 32 ±1
AD5378 14 ±8.75 V 32 ±3
AD5379 14 ±8.75 V 40 ±3