Datasheet

AD5362/AD5363
Rev. A | Page 25 of 28
Table 17. Address Codes for Data Readback
1
F15 F14 F13 F12 F11 F10 F9 F8 F7 Register Read
0 0 0 X1A register
0 0 1 X1B register
0 1 0 C register
0 1 1
Bit F12 to Bit F7 select the channel to be read back;
Channel 0 = 001000 to Channel 3 = 001011
Channel 4 = 010000 to Channel 7 = 010011
M register
1 0 0 0 0 0 0 0 1 Control register
1 0 0 0 0 0 0 1 0 OFS0 data register
1 0 0 0 0 0 0 1 1 OFS1 data register
1 0 0 0 0 0 1 0 0 Reserved
1 0 0 0 0 0 1 1 0
A/B Select Register 0
1 0 0 0 0 0 1 1 1
A/B Select Register 1
1 0 0 0 0 1 0 0 0 Reserved
1 0 0 0 0 1 0 0 1 Reserved
1 0 0 0 0 1 0 1 0 Reserved
1 0 0 0 0 1 0 1 1 GPIO read (data in F0)
2
1
Bit F6 to Bit F0 are don’t cares for the data readback function.
2
Bit F6 to Bit F0 should be 0 for GPIO read.
Table 18. DACs Selected by A/B Select Registers
Bits
1
A/B Select
Register
F7 F6 F5 F4 F3 F2 F1 F0
0 Reserved Reserved Reserved Reserved DAC 3 DAC 2 DAC 1 DAC 0
1 Reserved Reserved Reserved Reserved DAC 7 DAC 6 DAC 5 DAC 4
1
If the bit is set to 0, Register X2A is selected. If the bit is set to 1, Register X2B is selected.