8-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC AD5362/AD5363 FEATURES 8-channel DAC in 52-lead LQFP and 56-lead LFCSP packages Guaranteed monotonic to 16/14 bits Nominal output voltage range of −10 V to +10 V Multiple output voltage spans available Thermal shutdown function Channel monitoring multiplexer GPIO function System calibration function allowing user-programmable offset and gain Channel grouping and addressing features Data error checking feature SPI-compatible serial interface 2.
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AD5362/AD5363 TABLE OF CONTENTS Features .............................................................................................. 1 Reset Function ............................................................................ 20 Applications ....................................................................................... 1 Clear Function ............................................................................ 20 Functional Block Diagram ....................................................
AD5362/AD5363 GENERAL DESCRIPTION The AD5362/AD5363 contain eight 16-/14-bit DACs in a single 52-lead LQFP package or 56-lead LFCSP package. The devices provide buffered voltage outputs with a span of 4× the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility, the device is divided into two groups of four DACs, and the output range of each group can be independently adjusted by an offset DAC.
AD5362/AD5363 SPECIFICATIONS DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −4.5 V; VREF = 5 V; AGND = DGND = SIGGND0 = SIGGND1 = 0 V; RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
AD5362/AD5363 Parameter DIGITAL OUTPUTS (SDO, BUSY, GPIO, PEC) Output Low Voltage Output High Voltage (SDO) High Impedance Leakage Current High Impedance Output Capacitance2 TEMPERATURE SENSOR (TEMP_OUT)2 Accuracy Output Voltage at 25°C Output Voltage Scale Factor Output Load Current Power-On Time POWER REQUIREMENTS DVCC VDD VSS Power Supply Sensitivity2 ∆Full Scale/∆VDD ∆Full Scale/∆VSS ∆Full Scale/∆DVCC DICC IDD ISS Power-Down Mode DICC IDD ISS Power Dissipation Power Dissipation Unloaded (P) Junction Tem
AD5362/AD5363 AC CHARACTERISTICS DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF = 5 V; AGND = DGND = SIGGND0 = SIGGND1 = 0 V; CL = 200 pF; RL = 10 kΩ; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
AD5362/AD5363 TIMING CHARACTERISTICS DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; VREF = 5 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF to GND; RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted. Table 4. SPI Interface Parameter 1, 2, 3 t1 t2 t3 t4 t5 t6 t7 t8 t9 4 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 5 t23 Limit at TMIN, TMAX 20 8 8 11 20 10 5 5 42 1/1.
AD5362/AD5363 t1 SCLK 1 24 2 t3 t4 SYNC 24 t11 t6 t5 t7 SDI 1 t2 t8 DB0 DB23 t9 t10 BUSY t12 t13 LDAC1 t17 t14 VOUTx1 t15 t13 LDAC2 t17 VOUTx2 t16 CLR t18 VOUTx t19 RESET VOUTx t18 t20 BUSY 05762-004 t23 1 LDAC ACTIVE DURING BUSY. 2 LDAC ACTIVE AFTER BUSY. Figure 4. SPI Write Timing Rev.
AD5362/AD5363 t22 SCLK 48 t21 SYNC DB23 DB0 DB23 DB0 NOP CONDITION INPUT WORD SPECIFIES REGISTER TO BE READ DB0 SDO DB23 DB15 DB0 SELECTED REGISTER DATA CLOCKED OUT LSB FROM PREVIOUS WRITE Figure 5. SPI Read Timing OUTPUT VOLTAGE FULL-SCALE ERROR + ZERO-SCALE ERROR VMAX ACTUAL TRANSFER FUNCTION IDEAL TRANSFER FUNCTION 0 2N – 1 DAC CODE n = 16 FOR AD5362 n = 14 FOR AD5363 ZERO-SCALE ERROR 05762-006 VMIN Figure 6. DAC Transfer Function Rev.
AD5362/AD5363 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 60 mA do not cause SCR latch-up. Table 5.
AD5362/AD5363 56 55 54 53 52 51 50 49 48 47 46 45 44 43 CLR LDAC AGND DGND DVCC SDO PEC SDI SCLK SYNC DVCC DGND NC NC AGND DGND DVCC SDO PEC SDI SCLK SYNC DVCC DGND NC NC NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 52 51 50 49 48 47 46 45 44 43 42 41 40 39 NC 2 38 SIGGND0 PIN 1 INDICATOR 3 RESET BIN/2SCOMP BUSY GPIO MON_OUT MON_IN0 NC NC NC NC NC VDD VSS VREF1 37 VOUT3 36 VOUT2 4 35 VOUT1 AD5362/ AD5363 6 7 34 VOUT0 TOP VIEW (Not to Scale) 8 9 33 TEMP_OUT 32 MON_IN1 31 VREF0 10 30 NC
AD5362/AD5363 LQFP 33 Pin No. LFCSP 35 Mnemonic TEMP_OUT 38 40 SIGGND0 43, 51 45, 53 DGND 44, 50 46, 52 DVCC 45 47 SYNC 46 48 SCLK 47 49 SDI 48 50 PEC 49 51 SDO 52 54 AGND Exposed Paddle EP Description Provides an output voltage proportional to the chip temperature, typically 1.46 V at 25°C with an output variation of 4.4 mV/°C. Reference Ground for DAC 0 to DAC 3. VOUT0 to VOUT3 are referenced to this voltage. Ground for All Digital Circuitry.
AD5362/AD5363 TYPICAL PERFORMANCE CHARACTERISTICS 0.0050 2 0.0025 AMPLITUDE (V) 0 0 16384 32768 65535 49152 –0.0050 05762-008 0 DAC CODE 0 1 1.0 VDD = +15V VSS = –15V DVCC = +5V VREF = +3V 0.5 DNL (LSB) 0.5 INL ERROR (LSB) 5 4 Figure 12. Digital Crosstalk 1.0 0 0 –0.5 –0.5 20 40 05762-009 –1.0 0 80 60 TEMPERATURE (°C) 0 16384 0 32768 65535 49152 DAC CODE Figure 10. Typical INL Error vs. Temperature Figure 13.
AD5362/AD5363 0.50 14 VSS = –12V VDD = +12V VREF = +3V 12 NUMBER OF UNITS DICC (mA) 0.45 DVCC = +5.5V 0.40 DVCC = 5V TA = 25°C DVCC = +3.6V 0.35 DVCC = +2.5V 10 8 6 4 0.30 –20 0 20 40 80 60 TEMPERATURE (°C) 05762-014 0 0.25 –40 0.30 Figure 15. DICC vs. Temperature 0.35 0.45 0.40 DICC (mA) 05762-017 2 0.50 Figure 18. Typical DICC Distribution 2.0 6.5 1.9 IDD 1.8 1.7 VOLTAGE (V) IDD/ISS (mA) 6.0 5.5 ISS 1.6 1.5 1.4 1.3 5.0 1.
AD5362/AD5363 TERMINOLOGY Integral Nonlinearity (INL) Integral nonlinearity, or endpoint linearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error and is expressed in least significant bits (LSB). Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
AD5362/AD5363 THEORY OF OPERATION DAC ARCHITECTURE The AD5362/AD5363 contain eight DAC channels and eight output amplifiers in a single package. The architecture of a single DAC channel consists of a 16-bit (AD5362) or 14-bit (AD5363) resistor-string DAC followed by an output buffer amplifier. The resistor-string section is simply a string of resistors, of equal value, from VREF0 or VREF1 to AGND. This type of architecture guarantees DAC monotonicity.
AD5362/AD5363 X1A REGISTER X2A REGISTER MUX X1B REGISTER MUX X2B REGISTER DAC REGISTER DAC C REGISTER 05762-020 M REGISTER Figure 21. Data Registers Associated with Each DAC Channel Each DAC channel also has a gain (M) register and an offset (C) register, which allow trimming out of the gain and offset errors of the entire signal chain. Data from the X1A register is operated on by a digital multiplier and adder controlled by the contents of the M and C registers.
AD5362/AD5363 OUTPUT AMPLIFIER Because the output amplifiers can swing to 1.4 V below the positive supply and 1.4 V above the negative supply, this limits how much the output can be offset for a given reference voltage. For example, it is not possible to have a unipolar output range of 20 V, because the maximum supply voltage is ±16.5 V. The input code is the value in the X1A or X1B register that is applied to the DAC (X1A, X1B default code = 8192).
AD5362/AD5363 Reference Selection Example Reducing Full-Scale Error If Full-scale error can be reduced as follows: Nominal output range = 20 V (−10 V to +10 V) 1. 2. 3. Offset error = ±100 mV Gain error = ±3%, and SIGGND = AGND = 0 V 4. Then Gain error = ±3% => Maximum positive gain error = 3% => Output range including gain error = 20 + 0.03(20) = 20.6 V AD5362 Calibration Example Offset error = ±100 mV => Maximum offset error span = 2(100 mV) = 0.
AD5362/AD5363 RESET FUNCTION The reset function is initiated by the RESET pin. On the rising edge of RESET, the AD5362/AD5363 state machine initiates a reset sequence to reset the X, M, and C registers to their default values. This sequence typically takes 300 μs, and the user should not write to the part during this time. On power-up, it is recommended that the user bring RESET high as soon as possible to properly initialize the registers.
AD5362/AD5363 MONITOR FUNCTION The AD5362/AD5363 contain a channel monitor function that consists of an analog multiplexer addressed via the serial interface, allowing any channel output to be routed to the MON_OUT pin for monitoring using an external ADC. In addition, two monitor inputs, MON_IN0 and MON_IN1, are provided, which can also be routed to MON_OUT.
AD5362/AD5363 SERIAL INTERFACE The AD5362/AD5363 contain a high speed SPI operating at clock frequencies up to 50 MHz (20 MHz for read operations). To minimize both the power consumption of the device and on-chip digital noise, the interface powers up fully only when the device is being written to, that is, on the falling edge of SYNC. The serial interface is 2.5 V LVTTL-compatible when operating from a 2.5 V to 3.6 V DVCC supply.
AD5362/AD5363 PACKET ERROR CHECKING CHANNEL ADDRESSING AND SPECIAL MODES To verify that data has been received correctly in noisy environments, the AD5362/AD5363 offer the option of error checking based on an 8-bit (CRC-8) cyclic redundancy check. The device controlling the AD5362/AD5363 should generate an 8-bit checksum using the polynomial C(x) = x8 + x2 + x1 + 1. This is added to the end of the data-word, and 32 data bits are sent to the AD5362/AD5363 before taking SYNC high.
AD5362/AD5363 SPECIAL FUNCTION MODE If the mode bits are 00, the special function mode is selected, as shown in Table 15. Bit I21 to Bit I16 of the serial data-word select the special function, and the remaining bits are data required for execution of the special function, for example, the channel address for data readback. The codes for the special functions are shown in Table 16. Table 17 shows the addresses for data readback. Table 15.
AD5362/AD5363 Table 17.
AD5362/AD5363 APPLICATIONS INFORMATION The AD5362/AD5363 should have ample supply decoupling of 10 μF in parallel with 0.1 μF on each supply located as close to the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.
AD5362/AD5363 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 52 40 39 1 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7° 3.5° 0° SEATING PLANE 13 27 14 0.10 COPLANARITY VIEW A VIEW A 26 0.38 0.32 0.22 0.65 BSC LEAD PITCH 051706-A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCC Figure 27. 52-Lead Low Profile Quad Flat Package [LQFP] (ST-52) Dimensions shown in millimeters 8.00 BSC SQ 0.60 MAX 0.50 0.40 0.
AD5362/AD5363 ORDERING GUIDE Model AD5362BSTZ 1 AD5362BSTZ-REEL1 AD5362BCPZ1 AD5362BCPZ-REEL71 EVAL-AD5362EBZ1 AD5363BSTZ1 AD5363BSTZ-REEL1 AD5363BCPZ1 AD5363BCPZ-REEL71 EVAL-AD5363EBZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 52-Lead Low Profile Quad Flat Package [LQFP] 52-Lead Low Profile Quad Flat Package [LQFP] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip S
