Datasheet

AD5360/AD5361
Rev. A | Page 3 of 28
GENERAL DESCRIPTION
The AD5360/AD5361 contain sixteen, 16-/14-bit DACs in a
single 52-lead LQFP or 56-lead LFCSP package. They provide
buffered voltage outputs with a span four times the reference
voltage. The gain and offset of each DAC can be independently
trimmed to remove errors. For even greater flexibility, the device is
divided into two groups of eight DACs, and the output range of
each group can be independently adjusted by an offset DAC.
The AD5360/AD5361 offer guaranteed operation over a wide
supply range with V
SS
from −4.5 V to −16.5 V and V
DD
from
+8 V to +16.5 V. The output amplifier headroom requirement
is 1.4 V.
The AD5360/AD5361 have a high speed 4-wire serial interface,
which is compatible with SPI, QSPI™, MICROWIRE™, and DSP
interface standards and can handle clock speeds of up to
50 MHz. All the outputs can be updated simultaneously by
taking the
LDAC
input low. Each channel has a programmable
gain register and an offset adjust register.
Each DAC output is amplified and buffered on-chip with
respect to an external SIGGNDx input. The DAC outputs can
also be switched to SIGGNDx via the
CLR
pin.