Datasheet

AD5360/AD5361
Rev. A | Page 15 of 28
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE
The AD5360/AD5361 contain 16 DAC channels and 16 output
amplifiers in a single package. The architecture of a single DAC
channel consists of a 16-bit resistor-string DAC in the case of
the AD5360 and a 14-bit DAC in the case of the AD5361,
followed by an output buffer amplifier. The resistor-string
section is simply a string of resistors, of equal value, from
VREF0 or VREF1 to AGND. This type of architecture
guarantees DAC monotonicity. The 16-/14-bit binary digital
code loaded to the DAC register determines at which node
on the string the voltage is tapped off before being fed into
the output amplifier. The output amplifier multiplies the
DAC output voltage by 4. The nominal output span is 12 V
with a 3 V reference and 20 V with a 5 V reference.
CHANNEL GROUPS
The 16 DAC channels of the AD5360/AD5361 are arranged into
two groups of eight channels. The eight DACs of Group 0 derive
their reference voltage from VREF0. Group 1 derives its refer-
ence voltage from VREF1. Each group has its own signal
ground pin.
Table 6. AD5360/AD5361 Registers
Register Name Word Length in Bits Description
X1A (group) (channel) 16 (14) Input Data Register A, one for each DAC channel.
X1B (group) (channel) 16 (14) Input Data Register B, one for each DAC channel.
M (group) (channel) 16 (14) Gain trim register, one for each DAC channel.
C (group) (channel) 16 (14) Offset trim register, one for each DAC channel.
X2A (group) (channel) 16 (14)
Output Data Register A, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable or directly
writable.
X2B (group) (channel) 16 (14)
Output Data Register B, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable or directly
writable.
DAC (group) (channel)
Data registers from which the DACs take their final input data. The DAC registers are
updated from the X2A or X2B registers. They are not readable or directly writable.
OFS0 14 Offset DAC 0 data register, sets offset for Group 0.
OFS1 14 Offset DAC 1 data register, sets offset for Group 1.
Control 5 Control register.
Monitor 6 Monitor enable and configuration register.
GPIO 2 GPIO configuration register.
Table 7. AD5360/AD5361 Input Register Default Values
Register Name AD5360 Default Value AD5361 Default Value
X1A, X1B 0x8000 0x2000
M 0xFFFF 0x3FFF
C 0x8000 0x2000
OFS0, OFS1 0x2000 0x2000
Control 0x00 0x00
A/B Select 0 and A/B Select 1
0x00 0x00