6-Channel, 16-/14-Bit, Serial Input, Voltage-Output DAC AD5360/AD5361 FEATURES SPI-compatible serial interface 2.5 V to 5.
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AD5360/AD5361 TABLE OF CONTENTS Features .............................................................................................. 1 Reset Function ............................................................................ 19 Applications ....................................................................................... 1 Clear Function ............................................................................ 19 Functional Block Diagram ....................................................
AD5360/AD5361 GENERAL DESCRIPTION The AD5360/AD5361 contain sixteen, 16-/14-bit DACs in a single 52-lead LQFP or 56-lead LFCSP package. They provide buffered voltage outputs with a span four times the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility, the device is divided into two groups of eight DACs, and the output range of each group can be independently adjusted by an offset DAC.
AD5360/AD5361 SPECIFICATIONS DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −4.5 V; VREF = 5 V; AGND = DGND = SIGGND = 0 V; RL = open circuit; gain (M), offset (C), and DAC offset registers at default value; all specifications TMIN to TMAX, unless otherwise noted. Table 1.
AD5360/AD5361 Parameter DIGITAL OUTPUTS (SDO, BUSY, GPIO, PEC) Output Low Voltage Output High Voltage (SDO) High Impedance Leakage Current High Impedance Output Capacitance4 TEMPERATURE SENSOR (TEMP_OUT)4 Accuracy Output Voltage at 25°C Output Voltage Scale Factor Output Load Current Power-On Time POWER REQUIREMENTS DVCC VDD VSS Power Supply Sensitivity4 ∆ Full Scale/∆ VDD ∆ Full Scale/∆ VSS ∆ Full Scale/∆ DVCC DICC IDD ISS Power-Down Mode DICC IDD ISS Power Dissipation Power Dissipation Unloaded (P) Juncti
AD5360/AD5361 TIMING CHARACTERISTICS DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −8 V to −16.5 V; VREF = 5 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF to GND; RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted. Table 3. SPI Interface (See Figure 4 and Figure 5) Parameter 1, 2 t1 t2 t3 t4 t5 t6 t7 t8 t9 3 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 4 t23 Limit at TMIN, TMAX 20 8 8 11 20 10 5 5 42 1/1.
AD5360/AD5361 t1 SCLK 1 24 2 t3 t4 SYNC 24 t11 t6 t5 t7 SDI 1 t2 t8 DB0 DB23 t9 t10 BUSY t12 t13 LDAC1 t17 t14 VOUTx1 t15 t13 LDAC2 t17 VOUTx2 t16 CLR t18 VOUTx t19 RESET VOUTx t18 t20 BUSY 05761-010 t23 1 LDAC ACTIVE DURING BUSY. 2 LDAC ACTIVE AFTER BUSY. Figure 4. SPI Write Timing Rev.
AD5360/AD5361 t22 SCLK 48 t21 SYNC DB23 DB0 DB23 DB0 NOP CONDITION INPUT WORD SPECIFIES REGISTER TO BE READ DB0 SDO DB23 DB15 DB0 SELECTED REGISTER DATA CLOCKED OUT LSB FROM PREVIOUS WRITE Figure 5. SPI Read Timing OUTPUT VOLTAGE FULL-SCALE ERROR + ZERO-SCALE ERROR VMAX ACTUAL TRANSFER FUNCTION IDEAL TRANSFER FUNCTION 0 2N – 1 DAC CODE n = 16 FOR AD5360 n = 14 FOR AD5361 ZERO-SCALE ERROR 05761-001 VMIN Figure 6. DAC Transfer Function Rev.
AD5360/AD5361 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 60 mA do not cause SCR latch-up. Table 4.
AD5360/AD5361 CLR LDAC AGND DGND DVCC SDO PEC SDI SCLK SYNC DVCC DGND VOUT7 VOUT6 AGND DGND DVCC SDO PEC SDI SCLK SYNC DVCC DGND VOUT7 VOUT6 VOUT5 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 56 55 54 53 52 51 50 49 48 47 46 45 44 43 52 51 50 49 48 47 46 45 44 43 42 41 40 39 VOUT4 3 37 VOUT3 36 VOUT2 4 5 AD5360/ AD5361 6 7 TOP VIEW (Not to Scale) 8 35 VOUT1 34 VOUT0 33 TEMP_OUT 32 MON_IN1 9 31 VREF0 10 30 NC 11 29 VSS 28 VDD 12 27 NC 13 05761-022 NC VOUT8 VOUT9 VOUT10 VOUT11 SIGGND1
AD5360/AD5361 LQFP 38 Pin No. LFCSP 40 43, 51 45, 53 DGND 44, 50 46, 52 DVCC 45 47 SYNC 46 48 SCLK 47 49 SDI 48 50 PEC 49 51 SDO 52 54 AGND EP Connect to VSS Mnemonic SIGGND0 Description Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to this voltage. Ground for All Digital Circuitry. Both DGND pins should be connected to the DGND plane. Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
AD5360/AD5361 TYPICAL PERFORMANCE CHARACTERISTICS 2 0.0050 0.0025 AMPLITUDE (V) 0 0 32768 49152 –0.0050 05761-012 16384 0 65535 DAC CODE 0 1 Figure 12. Digital Crosstalk VDD = +15V VSS = –15V DVCC = +5V VREF = +3V 0.5 DNL (LSB) 0.5 INL ERROR (LSB) 5 4 1.0 1.0 0 0 –0.5 –0.5 20 40 05761-013 –1.0 0 80 60 TEMPERATURE (°C) 0 16384 32768 65535 49152 DAC CODE Figure 10. Typical INL Error vs. Temperature Figure 13.
AD5360/AD5361 6 0.50 VSS = –12V VDD = +12V VREF = +3V DVCC = 5V TA = 25°C 5 NUMBER OF UNITS DVCC = +5.5V 0.40 DVCC = +3.6V 0.35 DVCC = +2.5V 0.30 4 3 2 1 –20 0 20 40 60 80 TEMPERATURE (°C) 0 0.48 05761-018 0.25 –40 0.50 0.52 0.54 0.58 0.56 ICC (mA) Figure 15. ICC vs. Temperature 05761-021 ICC (mA) 0.45 Figure 18. Typical ICC Distribution 8.0 2.0 1.9 1.8 7.5 1.7 VOLTAGE (V) IDD/ISS (mA) IDD 7.0 ISS 1.6 1.5 1.4 1.3 6.5 1.
AD5360/AD5361 TERMINOLOGY Integral Nonlinearity (INL) Integral nonlinearity, or relative accuracy, is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error and is expressed in least significant bits (LSB). Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
AD5360/AD5361 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE CHANNEL GROUPS The AD5360/AD5361 contain 16 DAC channels and 16 output amplifiers in a single package. The architecture of a single DAC channel consists of a 16-bit resistor-string DAC in the case of the AD5360 and a 14-bit DAC in the case of the AD5361, followed by an output buffer amplifier. The resistor-string section is simply a string of resistors, of equal value, from VREF0 or VREF1 to AGND. This type of architecture guarantees DAC monotonicity.
AD5360/AD5361 A/B REGISTERS GAIN/OFFSET ADJUSTMENT X2A REGISTER MUX X1B REGISTER MUX X2B REGISTER DAC REGISTER DAC 05761-023 M REGISTER C REGISTER Figure 21. Data Registers Associated with Each DAC Channel Each DAC channel also has a gain register (M) and an offset (C) register, which allow trimming out of the gain and offset errors of the entire signal chain. Data from the X1A register is operated on by a digital multiplier and adder by the contents of the M and C registers.
AD5360/AD5361 OUTPUT AMPLIFIER Because the output amplifiers can swing to 1.4 V below the positive supply and 1.4 V above the negative supply, this limits how much the output can be offset for a given reference voltage. For example, it is not possible to have a unipolar output range of 20 V because the maximum supply voltage is ±16.5 V.
AD5360/AD5361 4. 5. Choose the new required VOUTMAX and VOUTMIN, keeping the VOUT limits centered on the nominal values. Note that VDD and VSS must provide sufficient headroom. Calculate the value of VREF as follows: VREF = (VOUTMAX − VOUTMIN)/4 Full-scale error can be reduced as follows: 1. 2. 3. Reference Selection Example 4. Nominal output range = 20 V (−10 V to +10 V) Offset error = ±100 mV Gain error = ±3% SIGGND = AGND = 0 V Measure the zero-scale error.
AD5360/AD5361 RESET FUNCTION The reset function is initiated by the RESET pin. On the rising edge of RESET, the AD5360/AD5361 state machine initiates a reset sequence to reset the X, M, and C registers to their default values. This sequence typically takes 300 μs, and the user should not write to the part during this time. On power-up, it is recommended that the user bring RESET high as soon as possible to properly initialize the registers.
AD5360/AD5361 MONITOR FUNCTION POWER-DOWN MODE The AD5360/AD5361 contain a channel monitor function that consists of an analog multiplexer addressed via the serial interface, allowing any channel output to be routed to this pin for monitoring using an external ADC. In addition, two monitor inputs, MON_IN0 and MON_IN1, are provided, which can also be routed to MON_OUT.
AD5360/AD5361 SERIAL INTERFACE The AD5360/AD5361 contain a high speed SPI operating at clock frequencies up to 50 MHz (20 MHz for read operations). To minimize both the power consumption of the device and on-chip digital noise, the interface powers up fully only when the device is being written to, that is, on the falling edge of SYNC. The serial interface is 2.5 V LVTTL-compatible when operating from a 2.5 V to 3.6 V DVCC supply.
AD5360/AD5361 SPI READBACK MODE PACKET ERROR CHECKING The AD5360/AD5361 allow data readback via the serial interface from every register directly accessible to the serial interface, which is all registers except the X2A, X2B, and DAC data registers. To read back a register, it is first necessary to tell the AD5360/AD5361 which register is to be read. This is achieved by writing a word whose first two bits are the Special Function Code 00 to the device.
AD5360/AD5361 CHANNEL ADDRESSING AND SPECIAL MODES If the mode bits are not 00, then the data word D15 to D0 (AD5360) or D13 to D0 (AD5361) is written to the device. Address Bit A4 to Address Bit A0 determine which channel or channels is/are written to, while the mode bits determine to which register (X1A, X1B, C, or M) the data is written, as shown in Table 10 and Table 11. Data is to be written to the X1A when the A/B bit in the control register is 0 or to the X1B register when the bit is 1.
AD5360/AD5361 SPECIAL FUNCTION MODE data required for execution of the special function, for example the channel address for data readback. If the mode bits are 00, then the special function mode is selected, as shown in Table 14. Bits I21 to I16 of the serial data word select the special function, while the remaining bits are The codes for the special functions in Table 16 show the addresses for data readback. Table 14.
AD5360/AD5361 Table 16.
AD5360/AD5361 INTERFACING EXAMPLES AD5360/ AD5361 SYNC SCK SCLK MOSI SDI MISO SDO PF10 RESET PF9 LDAC PF8 CLR PF7 BUSY ADSP-21065L 05761-024 ADSP-BF531 SPISELx The Analog Devices ADSP-21065L is a floating-point DSP with two serial ports (SPORTs). Figure 26 shows how one SPORT can be used to control the AD5360 or AD5361. In this example, the transmit frame synchronization (TFS) pin is connected to the receive frame synchronization (RFS) pin.
AD5360/AD5361 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 52 40 39 1 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7° 3.5° 0° SEATING PLANE 13 27 14 0.10 COPLANARITY VIEW A VIEW A 26 0.38 0.32 0.22 0.65 BSC LEAD PITCH 051706-A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCC Figure 27. 52-Lead Low Profile Quad Flat Package [LQFP] (ST-52) Dimensions shown in millimeters 8.00 BSC SQ 0.60 MAX 0.50 0.40 0.
AD5360/AD5361 NOTES ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05761-0-2/08(A) Rev.
