Datasheet
AD5346/AD5347/AD5348
Rev. 0 | Page 8 of 24
AD5347 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
AD5347
LDAC
A1
A0
WR
CS
AGND
V
OUT
D
V
REF
CD
V
REF
EF
V
REF
GH
V
OUT
C
V
OUT
B
V
OUT
A
V
REF
AB
PD
V
DD
DB
2
DB
3
DB
4
CLR
GAIN
DB
9
DB
8
DB
5
DB
6
DB
7
10-BIT
V
OUT
H
V
OUT
G
V
OUT
F
V
OUT
E
DGND
A2
RD
BUF
DB
0
DGND
DB
1
DGND
03331-0-007
Figure 7. AD5347 Pin Configuration—TSSOP
11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
40 39 38 37 36 35 34 33 32 31
LDAC
A1
A0
WR
CS
AGND
V
OUT
D
V
REF
CD
V
REF
EF
V
REF
GH
V
OUT
C
V
OUT
B
V
OUT
A
V
REF
AB
PD
V
DD
DB
2
DB
3
DB
4
CLR
GAIN
DB
9
DB
8
DB
5
DB
6
DB
7
V
OUT
H
V
OUT
G
V
OUT
F
V
OUT
E
DGND
A2
RD
BUF
AGND
V
DD
TOP VIEW
(Not to Scale)
AD5347
10-BIT
DB
1
DB
0
DGND
DGND
03331-0-008
Figure 8. AD5347 Pin Configuration—LFCSP
Table 6. AD5347 Pin Function Descriptions
Pin Number
TSSOP LFCSP Mnemonic Function
1 35 V
REF
GH Reference Input for DACs G and H.
2 36 V
REF
EF Reference Input for DACs E and F.
3 37 V
REF
CD Reference Input for DACs C and D.
4 38, 39 V
DD
Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both V
DD
pins on the LFCSP package
must be at the same potential.
5 40 V
REF
AB Reference Input for DACs A and B.
6–9,
11–14
1–4,
7–10
V
OUT
X Output of DAC X. Buffered output with rail-to-rail operation.
10 5, 6 AGND Analog Ground. Ground reference for analog circuitry.
15, 21–22
11,
17–18
DGND Digital Ground. Ground reference for digital circuitry.
16 12 BUF Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.
17 13
LDAC
Active Low Control Input. Updates the DAC registers with the contents of the input registers, which
allows all DAC outputs to be simultaneously updated.
18 14 A0 LSB Address Pin. Selects which DAC is to be written to.
19 15 A1 Address Pin. Selects which DAC is to be written to.
20 16 A2 MSB Address Pin. Selects which DAC is to be written to.
23–32 19–28 DB
0
–DB
9
Ten Parallel Data Inputs. DB
9
Is the MSB of these ten bits.
33 29
CS
Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or
with RD to read back data from a DAC.
34 30
RD
Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs.
35 31
WR
Active Low Write Input. Used in conjunction with CS to write data to the parallel interface.
36 32 GAIN Gain Control Pin. Controls whether the output range from the DAC is 0 V to V
REF
or 0 V to 2 × V
REF
.
37 33
CLR
Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.
38 34
PD
Power-Down Pin. This active low control pin puts all DACs into power-down mode.