Datasheet

AD5346/AD5347/AD5348
Rev. 0 | Page 5 of 24
TIMING CHARACTERISTICS
1, 2, 3
Table 3. V
DD
= 2.5 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted
Parameter Limit at T
MIN
, T
MAX
Unit Condition/Comments
Data Write Mode (Figure 3)
t
1
0 ns min
CS
to WR setup time
t
2
0 ns min
CS
to WR hold time
t
3
20 ns min
WR
pulse width
t
4
5 ns min Data, GAIN, BUF setup time
t
5
4.5 ns min Data, GAIN, BUF hold time
t
6
5 ns min
Synchronous mode. WR
falling to LDAC falling.
t
7
5 ns min
Synchronous mode. LDAC
falling to WR rising.
t
8
4.5 ns min Synchronous mode.
WR
rising to LDAC rising.
t
9
5 ns min
Asynchronous mode. LDAC
rising to WR rising.
t
10
4.5 ns min
Asynchronous mode. WR
rising to LDAC falling.
t
11
20 ns min
LDAC
pulse width
t
12
10 ns min
CLR
pulse width
t
13
20 ns min
Time between WR
cycles
t
14
20 ns min A0, A1, A2 setup time
t
15
0 ns min A0, A1, A2 hold time
Data Readback Mode (Figure 4)
t
16
0 ns min
A0, A1, A2 to
CS
setup time
t
17
0 ns min
A0, A1, A2 to
CS
hold time
t
18
0 ns min CS to falling edge of
RD
t
19
20 ns min
RD
pulse width; V
DD
= 3.6 V to 5.5 V
30 ns min
RD
pulse width; V
DD
= 2.5 V to 3.6 V
t
20
0 ns min
CS
to RD hold time
t
21
22 ns max
Data access time after falling edge of RD
; V
DD
= 3.6 V to 5.5 V
30 ns max
Data access time after falling edge of RD
V
DD
= 2.5 V to 3.6 V
t
22
4 ns min
Bus relinquish time after rising edge of RD
30 ns max
t
23
22 ns max
CS
falling edge to data; V
DD
= 3.6 V to 5.5 V
30 ns max
CS
falling edge to data; V
DD
= 2.5 V to 3.6 V
t
24
30 ns min
Time between
RD
cycles
t
25
30 ns min
Time from RD
to WR
t
26
30 ns min
Time from WR
to RD, V
DD
= 3.6 V to 5.5 V
50 ns min
Time from WR
to RD, V
DD
= 2.5 V to 3.6 V
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 2.
CS
WR
DATA,
GAIN, BUF
LDAC
1
LDAC
2
CLR
NOTES
1. SYNCHRONOUS LDAC UPDATE MODE
2. ASYNCHRONOUS LDAC UPDATE MODE
A0–A2
t
1
t
2
t
3
t
4
t
7
t
9
t
10
t
11
t
12
t
5
t
15
t
8
t
14
t
6
t
13
03331-0-003
CS
A0–A2
RD
WR
DATA
t
16
t
18
t
25
t
20
t
22
t
21
t
17
t
26
t
24
t
19
t
23
03331-0-004
Figure 3. Parallel Interface Write Timing Diagram Figure 4. Parallel Interface Read Timing Diagram