Datasheet

AD5346/AD5347/AD5348
Rev. 0 | Page 4 of 24
B Version
1
Parameter
2
Min Typ Max Unit Conditions/Comments
LOGIC OUTPUTS
6
V
DD
= 4.5 V to 5.5 V
Output Low Voltage, V
OL
0.4 V I
SINK
= 200 µA
Output High Voltage, V
OH
V
DD
– 1 V I
SOURCE
= 200 µA
V
DD
= 2.5 V to 3.6 V
Output Low Voltage, V
OL
0.4 V I
SINK
= 200 µA
Output High Voltage, V
OH
V
DD
– 0.5 V I
SOURCE
= 200 µA
POWER REQUIREMENTS
V
DD
2.5 5.5 V
I
DD
(Normal Mode) V
IH
= V
DD
, V
IL
= GND
V
DD
= 4.5 V to 5.5 V 1 1.65 mA All DACs in unbuffered mode. In buffered mode,
V
DD
= 2.5 V to 3.6 V 0.8 1.4 mA
extra current is typically x µA per DAC, where x = 5 µA +
V
REF
/R
DAC
I
DD
(Power-Down Mode) V
IH
= V
DD
, V
IL
= GND
V
DD
= 4.5 V to 5.5 V 0.4 1 µA
V
DD
= 2.5 V to 3.6 V 0.12 1 µA
See footnotes after the AC Characteristics table.
AC CHARACTERISTICS
6
Table 2. V
DD
= 2.5 V to 5.5 V; R
L
= 2 kΩ to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted
B Version
1
Parameter
2
Min Typ Max Unit Conditions/Comments
Output Voltage Settling Time V
REF
= 2 V
AD5346 6 8 µs 1/4 scale to 3/4 scale change (40 H to C0 H)
AD5347 7 9 µs 1/4 scale to 3/4 scale change (100 H to 300 H)
AD5348 8 10 µs 1/4 scale to 3/4 scale change (400 H to C00 H)
Slew Rate 0.7 V/µs
Major Code Transition Glitch
Energy
8 nV-s 1 LSB change around major carry
Digital Feedthrough 0.5 nV-s
Digital Crosstalk 1 nV-s
Analog Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3.5 nV-s
Multiplying Bandwidth 200 kHz V
REF
= 2 V ±0.1 V p-p; unbuffered mode
Total Harmonic Distortion –70 dB V
REF
= 2. V ±0.1 V p-p; frequency = 10 kHz; unbuffered mode
1
Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.
2
See Terminology section.
3
Linearity is tested using a reduced code range: AD5346 (Code 8 to 255); AD5347 (Code 28 to 1023); AD5348 (Code 115 to 4095).
4
DC specifications tested with outputs unloaded.
5
This corresponds to x codes. x = deadband voltage/LSB size.
6
Guaranteed by design and characterization, not production tested.
7
For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V
REF
= V
DD
and
the offset plus gain error must be positive.
I
OH
I
OL
TO OUTPUT
PIN
V
OH
(min) + V
OL
(max)
2
C
L
50pF
200µA
200µA
03331-0-002
Figure 2. Load Circuit for Digital Output Timing Specifications