Datasheet

REV. 0
AD5332/AD5333/AD5342/AD5343
–8–
AD5343 FUNCTIONAL BLOCK DIAGRAM
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.
.
.
.
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V
OUT
A
BUFFER
GND
AD5343
V
OUT
B
PD
LOW BYTE
REGISTER
V
DD
V
REF
HBEN
DB
7
DB
0
CS
WR
A0
CLR
LDAC
RESET
POWER-ON
RESET
HIGH BYTE
REGISTER
LOW BYTE
REGISTER
HIGH BYTE
REGISTER
POWER-DOWN
LOGIC
DAC
REGISTER
DAC
REGISTER
INTER-
FACE
LOGIC
BUFFER
12-BIT
DAC
12-BIT
DAC
AD5343 PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1 HBEN This pin is used when writing to the device to determine if data is written to the high byte register or the
low byte register.
2V
REF
Unbuffered reference input for both DACs.
3V
OUT
A Output of DAC A. Buffered output with rail-to-rail operation.
4V
OUT
B Output of DAC B. Buffered output with rail-to-rail operation.
5 GND Ground reference point for all circuitry on the part.
6 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
8 A0 Address pin for selecting between DAC A and DAC B.
9 CLR Asynchronous active low control input that clears all input registers and DAC registers to zeros.
10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. This allows
all DAC outputs to be simultaneously updated.
11 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
12 V
DD
Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 ␮F capacitor in parallel with a 0.1 ␮F capacitor to GND.
13–20 DB
0
–DB
7
Eight Parallel Data Inputs. DB
7
is the MSB of these eight bits.
AD5343 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD5343
LDAC
A0
WR
CS
GND
V
REF
V
OUT
B
V
OUT
A
PD
V
DD
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
12-BIT
CLR
HBEN