Datasheet

REV. 0
AD5332/AD5333/AD5342/AD5343
–12–
GAIN ERROR
V
DD
– Volts
ERROR – %
0.2
–0.6
01 3
0
–0.4
T
A
= 25
ⴰ
C
V
REF
= 2V
46
–0.5
–0.3
–0.2
–0.1
0.1
25
OFFSET ERROR
Figure 14. Offset Error and Gain
Error vs. V
DD
400
100
0
2.5 5.53.0 3.5 4.0 4.5 5.0
V
DD
– V
I
DD
– ␮A
200
300
T
A
= 25ⴗC
Figure 17. Supply Current vs. Supply
Voltage
CH1 1V
,
CH2 5V
,
TIME BASE = 5
␮
s/DIV
CH2
CH1
LDAC
V
OUT
V
DD
= 5V
T
A
= 25ⴗC
Figure 20. Half-Scale Settling (1/4 to
3/4 Scale Code Change)
5V SOURCE
SINK/SOURCE CURRENT – mA
V
OUT
– Volts
5
0
01 3
4
46
1
2
3
25
3V SOURCE
3V SINK
5V SINK
Figure 15. V
OUT
Source and Sink
Current Capability
0.5
0.1
0
2.5 5.53.0 3.5 4.0 4.5 5.0
V
DD
– V
I
DD
– ␮A
0.2
0.3
0.4
T
A
= 25ⴗC
Figure 18. Power-Down Current vs.
Supply Voltage
V
DD
CH1
CH2
V
OUT
A
T
A
= 25
ⴰ
C
V
DD
= 5V
V
REF
= 2V
CH1 2V, CH2 200mV, TIME BASE = 200␮s/DIV
Figure 21. Power-On Reset to 0 V
DAC CODE
400
50
0
ZERO-SCALE FULL-SCALE
I
DD
– ␮A
100
150
200
250
300
350
V
DD
= 3.6V
V
DD
= 5.5V
T
A
= 25ⴗC
V
REF
= 2V
Figure 16. Supply Current vs. DAC
Code
V
LOGIC
– V
1600
800
0
0
12345
I
DD
– ␮A
200
400
600
1000
1200
1400
T
A
= 25ⴗC
V
DD
= 5V
V
DD
= 3V
Figure 19. Supply Current vs. Logic
Input Voltage
CH1 500mV, CH2 5V, TIME BASE = 1␮s/DIV
CH1
CH2
T
A
= 25
ⴰ
C
V
DD
= 5V
V
REF
= 2V
V
OUT
A
PD
Figure 22. Exiting Power-Down to
Midscale