Datasheet
REV. 0
AD5332/AD5333/AD5342/AD5343
–6–
AD5333 FUNCTIONAL BLOCK DIAGRAM
POWER-ON
RESET
DAC
REGISTER
DAC
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INTER-
FACE
LOGIC
DB
9
DB
0
CS
WR
A0
CLR
LDAC
.
.
.
V
REF
A
RESET
V
REF
B
BUF
GAIN
10-BIT
DAC
10-BIT
DAC
V
OUT
A
BUFFER
AD5333
V
OUT
BBUFFER
V
DD
POWER-DOWN
LOGIC
PD
GND
AD5333 PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V
REF
or 0–2 V
REF
.
2 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
3V
REF
B Reference input for DAC B.
4V
REF
A Reference input for DAC A.
5V
OUT
A Output of DAC A. Buffered output with rail-to-rail operation.
6V
OUT
B Output of DAC B. Buffered output with rail-to-rail operation.
7 GND Ground reference point for all circuitry on the part.
8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
10 A0 Address pin for selecting between DAC A and DAC B.
11 CLR Asynchronous active-low control input that clears all input registers and DAC registers to zeros.
12 LDAC Active-low control input that updates the DAC registers with the contents of the input registers. This
allows all DAC outputs to be simultaneously updated.
13 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
14 V
DD
Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 F capacitor in parallel with a 0.1 F capacitor to GND.
15–24 DB
0
–DB
9
10 Parallel Data Inputs. DB
9
is the MSB of these 10 bits.
AD5333 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD5333
LDAC
A0
WR
CS
GAIN
V
REF
B
V
OUT
A
GND
PD
V
DD
DB
0
DB
1
DB
2
DB
7
DB
6
DB
3
DB
4
DB
5
10-BIT
V
OUT
B
V
REF
A
BUF
CLR
DB
8
DB
9