Datasheet

REV. 0
AD5332/AD5333/AD5342/AD5343
–15–
High-Byte Enable Input (HBEN)
High-Byte Enable is a control input on the AD5343 only that
determines if data is written to the high-byte input register or
the low-byte input register.
The low data byte of the AD5343 consists of data bits 0 to 7 at
data inputs DB
0
to DB
7
, while the high byte consists of data
bits 8 to 11 at data inputs DB
0
to DB
3
. DB
4
to DB
7
are ignored
during a high byte write, but they may be used for data to
set up the reference input as buffered/unbuffered, and buffer
amplifier gain. See Figure 32.
DB8DB9
XX
HIGH BYTE
LOW BYTE
X = UNUSED BIT
DB0DB1
DB2
DB3
DB4DB5
DB6DB7
XX
DB10DB11
Figure 30. Data Format for AD5343
POWER-ON RESET
The AD5332/AD5333/AD5342/AD5343 are provided with a
power-on reset function, so that they power up in a defined state.
The power-on state is:
• Normal operation
• Reference input unbuffered
•0 – V
REF
output range
• Output voltage set to 0 V
Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
POWER-DOWN MODE
The AD5332/AD5333/AD5342/AD5343 have low power con-
sumption, dissipating typically 0.69 mW with a 3 V supply and
1.5 mW with a 5 V supply. Power consumption can be further
reduced when the DACs are not in use by putting them into
power-down mode, which is selected by taking pin PD low.
When the PD pin is high, the DACs work normally with a typical
power consumption of 300 µA at 5 V (230 µA at 3 V). In power-
down mode, however, the supply current falls to 200 nA at 5 V
(80 nA at 3 V) when both DACs are powered down. Not only
does the supply current drop, but the output stage is also internally
switched from the output of the amplifier, making it open-circuit.
This has the advantage that the outputs are three-state while
the part is in power-down mode, and provides a defined input
condition for whatever is connected to the outputs of the DAC
amplifiers. The output stage is illustrated in Figure 31.
RESISTOR
STRING DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
VOUT
Figure 31. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 µs for V
DD
= 5 V and 5 µs when
V
DD
= 3 V. This is the time from a rising edge on the PD pin to
when the output voltage deviates from its power-down voltage.
See Figure 22.
Table I. AD5332/AD5333/AD5342 Truth Table
CLR LDAC CS WR A0 Function
111XXNo Data Transfer
1 1 X 1 X No Data Transfer
0 X X X X Clear All Registers
1100➝1 0 Load DAC A Input Register
1100➝1 1 Load DAC B Input Register
1 0 X X X Update DAC Registers
X = don’t care.
Table II. AD5343 Truth Table
CLR LDAC CS WR A0 HBEN Function
1 1 1 X X X No Data Transfer
1 1 X 1 X X No Data Transfer
0 X X X X X Clear All Registers
11 0 0➝1 0 0 Load DAC A Low Byte Input Register
11 0 0➝1 0 1 Load DAC A High Byte Input Register
11 0 0➝1 1 0 Load DAC B Low Byte Input Register
11 0 0➝1 1 1 Load DAC B High Byte Input Register
1 0 X X X X Update DAC Registers
X = don’t care.