Datasheet
REV. 0
AD5332/AD5333/AD5342/AD5343
–13–
I
DD
– A
FREQUENCY
0
100 150 400200 250 350300
V
DD
= +5V
V
DD
= +3V
Figure 23. I
DD
Histogram with V
DD
= 3
V and V
DD
= 5 V
–0.4
0612345
V
REF
– V
FULL-SCALE ERROR – %FSR
–0.2
0
0.2
T
A
= 25ⴗC
V
REF
= 2V
Figure 26. Full-Scale Error vs. V
REF
500 ns/DIV
0.939
0.938
0.937
0.936
0.935
0.934
0.933
0.932
0.931
0.930
0.929
V
OUT
– Volts
Figure 24. AD5342 Major-Code Tran-
sition Glitch Energy
4mV/DIV
750ns/DIV
Figure 27. DAC-DAC Crosstalk
FREQUENCY – kHz
10
–40
0.01
–20
–30
0
–10
dB
0.1 1 10 100 1k 10k
–50
–60
Figure 25. Multiplying Bandwidth
(Small-Signal Frequency Response)
FUNCTIONAL DESCRIPTION
The AD5332/AD5333/AD5342/AD5343 are dual DACs fabri-
cated on a CMOS process with resolutions of 8, 10, 12, and
12 bits, respectively. They are written to using a parallel inter-
face. They operate from single supplies of 2.5 V to 5.5 V and
the output buffer amplifiers offer rail-to-rail output swing. The
AD5333 and AD5342 have reference inputs that may be buff-
ered to draw virtually no current from the reference source.
Their output voltage range may be configured to be 0 to V
REF
or 0 to 2 V
REF
. The reference inputs of the AD5332 and AD5343
are unbuffered and their output range is 0 to V
REF
. The devices
have a power-down feature that reduces current consumption to
only 80 nA @ 3 V.
Digital-to-Analog Section
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the V
REF
pin provides the reference
voltage for the DAC. Figure 28 shows a block diagram of the
DAC architecture. Since the input coding to the DAC is straight
binary, the ideal output voltage is given by:
VV
D
Gain
OUT REF
N
=××
2
where:
D = decimal equivalent of the binary code which is loaded to
the DAC register:
0–255 for AD5332 (8 Bits)
0–1023 for AD5333 (10 Bits)
0–4095 for AD5342/AD5343 (12 Bits)
N = DAC resolution
Gain = Output Amplifier Gain (1 or 2)
V
OUT
GAIN
V
REF
BUF
DAC
REGISTER
INPUT
REGISTER
RESISTOR
STRING
OUTPUT
BUFFER AMPLIFIER
REFERENCE
BUFFER
Figure 28. Single DAC Channel Architecture