Datasheet

AD5337/AD5338/AD5339
Rev. C | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
0
3756-003
V
DD
1
V
OUT
A 2
V
OUT
B 3
REFIN 4
A0
8
SCL 7
SDA 6
GND 5
TOP VIEW
(Not to Scale)
AD5337/
AD5338/
AD5339
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 V
DD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND.
2 V
OUT
A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
3 V
OUT
B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
4 REFIN Reference Input Pin for the Two DACs. It has an input range from 0.25 V to V
DD
.
5 GND Ground Reference Point for All Circuitry on the Parts.
6 SDA
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input shift
register. SDA is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor.
7 SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input shift
register. Clock rates of up to 400 kbps can be accommodated in the 2-wire interface.
8 A0 Address Input. Sets the least significant bit of the 7-bit slave address.