Datasheet

AD5337/AD5338/AD5339
Rev. C | Page 6 of 28
TIMING CHARACTERISTICS
V
DD
= 2.5 V to 5.5 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Limit at T
MIN
, T
MAX
Parameter A Version and B Version Unit Conditions/Comments
f
SCL
400 kHz max SCL clock frequency
t
1
2.5 μs min SCL cycle time
t
2
0.6 μs min t
HIGH
, SCL high time
t
3
1.3 μs min t
LOW
, SCL low time
t
4
0.6 μs min t
HD, STA
, start/repeated start condition hold time
t
5
100 ns min t
SU, DAT
, data setup time
t
6
1
0.9 μs max t
HD, DAT
, data hold time
0 μs min t
HD, DAT
, data hold time
t
7
0.6 μs min t
SU, STA
, setup time for repeated start
t
8
0.6 μs min t
SU, STO
, stop condition setup time
t
9
1.3 μs min t
BUF
, bus free time between a stop and a start condition
t
10
300 ns max t
R
, rise time of SCL and SDA when receiving
0 ns min t
R
, rise time of SCL and SDA when receiving (CMOS compatible)
t
11
250 ns max t
F
, fall time of SDA when transmitting
0 ns min t
F
, fall time of SDA when receiving (CMOS compatible)
300 ns max t
F
, fall time of SCL and SDA when receiving
20 + 0.1 C
B
2
ns min t
F
, fall time of SCL and SDA when transmitting
C
B
400 pF max Capacitive load for each bus line
1
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V
IH
min of the SCL signal) to bridge the undefined region of SCL’s falling edge.
2
C
B
is the total capacitance of one bus line in pF; t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
t
9
t
3
t
4
t
6
t
2
t
5
t
7
t
8
t
1
t
4
t
11
t
10
0
3756-002
SDA
SCL
START
CONDITION
STOP
CONDITION
REPEATED
START
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram