Datasheet
REV. 0
AD5334/AD5335/AD5336/AD5344
–7–
AD5336 FUNCTIONAL BLOCK DIAGRAM
V
OUT
A
BUFFER
GND
AD5336
V
OUT
B
BUFFER
V
OUT
C
BUFFER
V
OUT
D
BUFFER
POWER-ON
RESET
TO ALL DACS
AND BUFFERS
POWER-DOWN
LOGIC
PD
DAC
REGISTER
INPUT
REGISTER
V
REF
C
INTER-
FACE
LOGIC
V
DD
V
REF
B
GAIN
DB
9
DB
0
CS
WR
A0
A1
CLR
LDAC
.
.
.
V
REF
A
V
REF
D
RESET
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
AD5336 PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1V
REF
D Unbuffered Reference Input for DAC D.
2V
REF
C Unbuffered Reference Input for DAC C.
3V
REF
B Unbuffered Reference Input for DAC B.
4V
REF
A Unbuffered Reference Input for DAC A.
5V
OUT
A Output of DAC A. Buffered output with rail-to-rail operation.
6V
OUT
B Output of DAC B. Buffered output with rail-to-rail operation.
7V
OUT
C Output of DAC C. Buffered output with rail-to-rail operation.
8V
OUT
D Output of DAC D. Buffered output with rail-to-rail operation.
9 GND Ground Reference Point for All Circuitry on the Part.
10 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
11 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
12 A0 LSB Address Pin for Selecting which DAC Is to Be Written to.
13 A1 MSB Address Pin for Selecting which DAC is to Be Written to.
14 LDAC Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers.
This allows all DAC outputs to be simultaneously updated.
15 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
16 V
DD
Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
17–26 DB
0
–DB
9
10 Parallel Data Inputs. DB
9
is the MSB of these 10 bits.
27 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V
REF
or 0–2 V
REF
.
28 CLR Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros.
AD5336 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD5336
LDAC
A1
A0
WR
CS
GND
V
OUT
D
V
REF
C
V
REF
B
V
REF
A
V
OUT
C
V
OUT
B
V
OUT
A
V
REF
D
PD
V
DD
DB
0
DB
1
DB
2
DB
3
DB
4
CLR
GAIN
DB
9
DB
8
DB
5
DB
6
DB
7
10-BIT