Datasheet
REV. 0
AD5334/AD5335/AD5336/AD5344
–6–
AD5335 FUNCTIONAL BLOCK DIAGRAM
.
.
.
.
.
.
V
OUT
A
BUFFER
GND
AD5335
V
OUT
B
V
OUT
C
V
OUT
D
TO ALL DACS
AND BUFFERS
POWER-DOWN
LOGIC
PD
DAC
REGISTER
V
REF
C/D
INTER-
FACE
LOGIC
V
DD
V
REF
A/B
HBEN
DB
7
DB
0
CS
WR
A0
A1
CLR
LDAC
RESET
POWER-ON
RESET
HIGH BYTE
REGISTER
BUFFER
BUFFER
BUFFER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
LOW BYTE
REGISTER
HIGH BYTE
REGISTER
HIGH BYTE
REGISTER
HIGH BYTE
REGISTER
LOW BYTE
REGISTER
LOW BYTE
REGISTER
LOW BYTE
REGISTER
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
AD5335 PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1V
REF
C/D Unbuffered Reference Input for DACs C and D.
2V
REF
A/B Unbuffered Reference Input for DACs A and B.
3V
OUT
A Output of DAC A. Buffered output with rail-to-rail operation.
4V
OUT
B Output of DAC B. Buffered output with rail-to-rail operation.
5V
OUT
C Output of DAC C. Buffered output with rail-to-rail operation.
6V
OUT
D Output of DAC D. Buffered output with rail-to-rail operation.
7 GND Ground Reference Point for All Circuitry on the Part.
8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
10 A0 LSB Address Pin for Selecting which DAC Is to Be Written to.
11 A1 MSB Address Pin for Selecting which DAC Is to Be Written to.
12 LDAC Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers.
This allows all DAC outputs to be simultaneously updated.
13 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
14 V
DD
Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
15–22 DB
0
–DB
7
Eight Parallel Data Inputs. DB
7
is the MSB of these eight bits.
23 HBEN This pin is used when writing to the device to determine if data is written to the high byte register or the
low byte register.
24 CLR Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros.
AD5335 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD5335
LDAC
A1
A0
WR
CS
V
REF
C/D
V
REF
A/B
V
OUT
A
V
OUT
B
GND
V
OUT
D
V
OUT
C
PD
V
DD
DB
0
DB
1
DB
2
CLR
HBEN
DB
7
DB
6
DB
3
DB
4
DB
5
10-BIT