Datasheet
REV. 0
–3–
AD5334/AD5335/AD5336/AD5344
AC CHARACTERISTICS
1
B Version
3
Parameter
2
Min Typ Max Unit Conditions/Comments
Output Voltage Settling Time V
REF
= 2 V. See Figure 20
AD5334 6 8 µs 1/4 Scale to 3/4 Scale Change (40 H to C0 H)
AD5335 7 9 µs 1/4 Scale to 3/4 Scale Change (100 H to 300 H)
AD5336 7 9 µs 1/4 Scale to 3/4 Scale Change (100 H to 300 H)
AD5344 8 10 µs 1/4 Scale to 3/4 Scale Change (400 H to C00 H)
Slew Rate 0.7 V/µs
Major Code Transition Glitch Energy 8 nV-s 1 LSB Change Around Major Carry
Digital Feedthrough 0.5 nV-s
Digital Crosstalk 3 nV-s
Analog Crosstalk 0.5 nV-s
DAC-to-DAC Crosstalk 3.5 nV-s
Multiplying Bandwidth 200 kHz V
REF
= 2 V ± 0.1 V p-p. Unbuffered Mode
Total Harmonic Distortion –70 dB V
REF
= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See Terminology section.
3
Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2, 3
Parameter Limit at T
MIN
, T
MAX
Unit Condition/Comments
t
1
0 ns min CS to WR Setup Time
t
2
0 ns min CS to WR Hold Time
t
3
20 ns min WR Pulsewidth
t
4
5 ns min Data, GAIN, HBEN Setup Time
t
5
4.5 ns min Data, GAIN, HBEN Hold Time
t
6
5 ns min Synchronous Mode. WR Falling to LDAC Falling.
t
7
5 ns min Synchronous Mode. LDAC Falling to WR Rising.
t
8
4.5 ns min Synchronous Mode. WR Rising to LDAC Rising.
t
9
5 ns min Asynchronous Mode. LDAC Rising to WR Rising.
t
10
4.5 ns min Asynchronous Mode. WR Rising to LDAC Falling.
t
11
20 ns min LDAC Pulsewidth
t
12
20 ns min CLR Pulsewidth
t
13
50 ns min Time Between WR Cycles
t
14
20 ns min A0, A1 Setup Time
t
15
0 ns min A0, A1 Hold Time
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
)
and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 1.
Specifications subject to change without notice.
(V
DD
= 2.5 V to 5.5 V. R
L
= 2 k⍀ to GND; C
L
= 200 pF to GND. All specifications T
MIN
to T
MAX
unless other-
wise noted.)
t
15
t
14
t
8
CS
WR
DATA,
GAIN,
HBEN
LDAC
1
LDAC
2
CLR
NOTES:
1
SYNCHRONOUS LDAC UPDATE MODE
2
ASYNCHRONOUS LDAC UPDATE MODE
A0,
A1
t
1
t
2
t
5
t
3
t
13
t
4
t
7
t
6
t
9
t
10
t
11
t
12
Figure 1. Parallel Interface Timing Diagram
(V
DD
= 2.5 V to 5.5 V, All specifications T
MIN
to T
MAX
unless otherwise noted.)