Datasheet

REV. 0
AD5334/AD5335/AD5336/AD5344
13
I
DD
A
FREQUENCY
300 350 600400 450 500 550
V
DD
= 5VV
DD
= 3V
Figure 23. I
DD
Histogram with V
DD
=
3 V and V
DD
= 5 V
FULL-SCALE ERROR %FSR
0
0.2
0
1
23456
V
DD
= 5V
T
A
= 25
C
V
REF
V
0.1
0.1
0.2
0.3
0.4
Figure 26. Full-Scale Error vs. V
REF
500ns/DIV
V
OUT
Volts
0.919
0.920
0.921
0.922
0.923
0.924
0.925
0.926
0.927
0.928
0.929
Figure 24. AD5344 Major-Code Tran-
sition Glitch Energy
750ns/DIV
1mV/DIV
Figure 27. DAC-DAC Crosstalk
FREQUENCY kHz
10
40
0.01
20
30
0
10
dB
0.1 1 10 100 1k 10k
50
60
Figure 25. Multiplying Bandwidth
(Small-Signal Frequency Response)
FUNCTIONAL DESCRIPTION
The AD5334/AD5335/AD5336/AD5344 are quad resistor-
string DACs fabricated on a CMOS process with resolutions of
8, 10, 10, and 12 bits, respectively. They are written to using a
parallel interface. They operate from single supplies of 2.5 V to
5.5 V and the output buffer amplifiers offer rail-to-rail output
swing. The gain of the buffer amplifiers in the AD5334 and
AD5336 can be set to 1 or 2 to give an output voltage range of
0 to V
REF
or 0 to 2 V
REF
. The AD5335 and AD5344 have out-
put buffers with unity gain.
The devices have a power-down feature that reduces current
consumption to only 80 nA @ 3 V.
Digital-to-Analog Section
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the V
REF
pin provides the reference
voltage for the DAC. Figure 28 shows a block diagram of the
DAC architecture. Since the input coding to the DAC is
straight binary, the ideal output voltage is given by:
VV
D
Gain
OUT REF
N
×
2
where:
D = decimal equivalent of the binary code which is loaded to
the DAC register:
0–255 for AD5334 (8 Bits)
0–1023 for AD5335/AD5336 (10 Bits)
0–4095 for AD5344 (12 Bits)
N = DAC resolution
Gain = Output Amplifier Gain (1 or 2)
V
OUT
GAIN
DAC
REGISTER
INPUT
REGISTER
RESISTOR
STRING
OUTPUT
BUFFER AMPLIFIER
V
REF
Figure 28. Single DAC Channel Architecture