Datasheet

REV. 0
AD5334/AD5335/AD5336/AD5344
–12–
GAIN ERROR
V
DD
– Volts
ERROR – %
0.2
–0.6
01 3
0
–0.4
T
A
= 25ⴗC
V
REF
= 2V
46
–0.5
–0.3
–0.2
–0.1
0.1
25
OFFSET ERROR
Figure 14. Offset Error and Gain
Error vs. V
DD
0
T
A
= 25ⴗC
I
DD
– ␮A
V
DD
– V
2.5 3.0 3.5 4.0 4.5 5.0 5.5
100
200
300
400
500
600
Figure 17. Supply Current vs. Supply
Voltage
V
OUT
A
5µs
CH1
CH2
LDAC
T
A
= 25ⴗC
V
DD
= 5V
V
REF
= 5V
CH1 1V, CH2 5V, TIME BASE= 1␮s/DIV
Figure 20. Half-Scale Settling (1/4 to
3/4 Scale Code Change)
5V SOURCE
SINK/SOURCE CURRENT – mA
V
OUT
– Volts
5
0
01 3
4
46
1
2
3
25
3V SOURCE
3V SINK
5V SINK
Figure 15. V
OUT
Source and Sink
Current Capability
0
2.5
I
DD
– ␮A
V
DD
– V
3.0 3.5 4.0 4.5 5.0 5.5
0.1
0.2
0.3
0.4
0.5
T
A
= 25ⴗC
Figure 18. Power-Down Current vs.
Supply Voltage
V
DD
CH1
CH2
V
OUT
A
T
A
= 25ⴗC
V
DD
= 5V
V
REF
= 2V
CH1 2V, CH2 200mV, TIME BASE = 200␮s/DIV
Figure 21. Power-On Reset to 0 V
0
ZERO-SCALE FULL SCALE
DAC CODE
I
DD
– ␮A
V
DD
= 5.5V
V
DD
= 3.6V
100
200
300
400
500
600
T
A
= 25 ⴗ C
V
REF
= 2V
Figure 16. Supply Current
vs. DAC Code
V
LOGIC
– V
I
DD
– ␮A
200
0
0
1
2345
400
600
800
1000
1200
1400
1600
1800
V
DD
= 5V
V
DD
= 3V
Figure 19. Supply Current
vs. Logic Input Voltage
CH1 500mV, CH2 5V, TIME BASE = 1␮s/DIV
CH1
CH2
T
A
= 25 ⴗ C
V
DD
= 5V
V
REF
= 2V
V
OUT
A
PD
Figure 22. Exiting Power-Down
to Midscale