Datasheet

AD5330/AD5331/AD5340/AD5341
Rev. A | Page 9 of 28
BUFFER
12-BIT
DAC
DAC
REGISTER
INPUT
REGISTER
POWER-DOWN
LOGIC
CS
WR
CLR
LDAC
V
REF
V
DD
V
OUT
PD GND
AD5340
POWER-ON
RESET
RESET
12
11
9
8
4 14
5
13 7
06852-007
DB
10
DB
9
DB
0
.
.
15
24
1
DB
11
2
BUF
3
GAIN
10
INTERFACE LOGIC
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
DB
10
PD
V
DD
DB
0
DB
1
DB
2
DB
7
DB
6
DB
3
DB
4
DB
5
12-BIT
AD5340
TOP VIEW
(Not to Scale)
DB
8
DB
9
DB
11
LDAC
GND
BUF
V
OUT
NC
V
REF
CS
WR
GAIN
CLR
06852-008
Figure 7. AD5340 Functional Block Diagram Figure 8. AD5340 Pin Configuration
Table 7. AD5340 Pin Function Descriptions
Pin No. Mnemonic Description
1 DB
10
Parallel Data Input.
2 DB
11
Most Significant Bit of Parallel Data Input.
3 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
4 V
REF
Reference Input.
5 V
OUT
Output of DAC. Buffered output with rail-to-rail operation.
6 NC No Connect.
7 GND Ground reference point for all circuitry on the part.
8
CS
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
9
WR
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
10 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V
REF
or 0 V to 2 × V
REF
.
11
CLR
Asynchronous active low control input that clears all input registers and DAC registers to zero.
12
LDAC
Active low control input that updates the DAC registers with the contents of the input registers.
13
PD
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
14 V
DD
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
15 to 24 DB
0
to DB
9
Ten Parallel Data Inputs.