Datasheet

AD5330/AD5331/AD5340/AD5341
Rev. A | Page 8 of 28
BUFFER
10-BIT
DAC
DAC
REGISTER
INPUT
REGISTER
INTERFACE LOGIC
POWER-DOWN
LOGIC
DB
8
DB
7
DB
0
.
.
CS
WR
CLR
LDAC
V
REF
V
DD
V
OUT
PD GND
AD5331
POWER-ON
RESET
RESET
10
9
7
6
13
20
1
DB
9
2
GAIN
8
3 12
4
11 5
06852-005
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
LDAC
GAIN
WR
CS
GND
V
REF
V
OUT
CLR
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
V
DD
PD
TOP VIEW
(Not to Scale)
AD5331
10-BIT
DB
8
DB
9
06852-006
Figure 5. AD5331 Functional Block Diagram Figure 6. AD5331 Pin Configuration
Table 6. AD5331 Pin Function Descriptions
Pin No. Mnemonic Description
1 DB
8
Parallel Data Input.
2 DB
9
Most Significant Bit of Parallel Data Input.
3 V
REF
Unbuffered Reference Input.
4 V
OUT
Output of DAC. Buffered output with rail-to-rail operation.
5 GND Ground reference point for all circuitry on the part.
6
CS
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
7
WR
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V
REF
or 0 V to 2 × V
REF
.
9
CLR
Active low control input that clears all input registers and DAC registers to zero.
10
LDAC
Active low control input that updates the DAC registers with the contents of the input registers.
11
PD
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
12 V
DD
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
13 to 20 DB
0
to DB
7
Eight Parallel Data Inputs.