Datasheet

AD5330/AD5331/AD5340/AD5341
Rev. A | Page 19 of 28
POWER-DOWN MODE
The AD5330/AD5331/AD5340/AD5341 have low power
consumption, dissipating only 0.35 mW with a 3 V supply and
0.7 mW with a 5 V supply. Power consumption can be further
reduced when the DAC is not in use by putting it into power-
down mode, which is selected by taking Pin
PD
low.
When the
PD
pin is high, the DAC works normally with a
typical power consumption of 140 μA at 5 V (115 μA at 3 V).
In power-down mode, however, the supply current falls to
200 nA at 5 V (80 nA at 3 V) when the DAC is powered down.
Not only does the supply current drop, but the output stage
is also internally switched from the output of the amplifier,
making it open-circuit. This has the advantage that the output
is three-state while the part is in power-down mode and provides
a defined input condition for whatever is connected to the
output of the DAC amplifier. The output stage is illustrated in
. Figure 39
RESISTOR
STRING DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
V
OUT
06852-040
Figure 39. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 μs for V
DD
= 5 V and 5 μs when
V
DD
= 3 V. This is the time from a rising edge on the
PD
pin to
when the output voltage deviates from its power-down voltage
(see ). Figure 31
Table 9. AD5330/AD5331/AD5340 Truth Table
1
CLR LDAC CS
WR
Function
1 1 1 X No data transfer
1 1 X 1 No data transfer
0 X X X
Clear all registers
1 1 0
0→1
Load input register
1 0 0
0→1
Load input register and DAC register
1 0 X X Update DAC register
1
X = don’t care.
Table 10. AD5341 Truth Table
1
CLR LDAC CS WR
HBEN Function
1 1 1 X X No data transfer
1 1 X 1 X No data transfer
0 X X X X
Clear all registers
1 1 0
0→1
0
Load low byte input register
1 1 0
0→1
1
Load high byte input register
1 0 0
0→1
0
Load low byte input register and DAC register
1 0 0
0→1
1
Load high byte input register and DAC register
1 0 X X X Update DAC register
1
X = don’t care.