Datasheet

AD5330/AD5331/AD5340/AD5341
Rev. A | Page 10 of 28
BUFFER
12-BIT
DAC
DAC
REGISTER
LOW BYTE
REGISTER
INTERFACE LOGIC
POWER-DOWN
LOGIC
BUF
DB
7
DB
0
.
.
HBEN
CS
WR
CLR
LDAC
V
REF
V
DD
V
OUT
PD GND
AD5341
POWER-ON
RESET
RESET
9
7
6
1
13
20
2
GAIN
8
3 12
4
11 5
HIGH BYTE
REGISTER
10
06852-009
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
LDAC
GAIN
WR
CS
GND
V
REF
V
OUT
CLR
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
V
DD
PD
TOP VIEW
(Not to Scale)
AD5341
10-BIT
HBEN
BUF
06852-010
Figure 9. AD5341 Functional Block Diagram Figure 10. AD5341 Pin Configuration
Table 8. AD5341 Pin Function Descriptions
Pin No. Mnemonic Description
1 HBEN
High Byte Enable Pin. This pin is used when writing to the device to determine if data is written to the high
byte register or the low byte register.
2 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
3 V
REF
Reference Input.
4 V
OUT
Output of DAC. Buffered output with rail-to-rail operation.
5 GND Ground reference point for all circuitry on the part.
6
CS
Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
7
WR
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V
REF
or 0 V to 2 × V
REF
.
9
CLR
Asynchronous active low control input that clears all input registers and DAC registers to zero.
10
LDAC
Active low control input that updates the DAC registers with the contents of the input registers.
11
PD
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
12 V
DD
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
13 to 20 DB
0
to DB
7
Eight Parallel Data Inputs. DB
7
is the MSB of these eight bits.