Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 20

2.5 V to 5.5 V, 115 μA, Parallel Interface

Single Voltage-Output 8-/10-/12-Bit DACs

AD5330/AD5331/AD5340/AD5341

Rev. A

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FEATURES

AD5330: single 8-bit DAC in 20-lead TSSOP

AD5331: single 10-bit DAC in 20-lead TSSOP

AD5340: single 12-bit DAC in 24-lead TSSOP

AD5341: single 12-bit DAC in 20-lead TSSOP

Low power operation: 115 μA @ 3 V, 140 μA @ 5 V

Power-down to 80 nA @ 3 V, 200 nA @ 5 V via

2.5 V to 5.5 V power supply

Double-buffered input logic

Guaranteed monotonic by design over all codes

Buffered/unbuffered reference input options

Output range: 0 V to V

REF

or 0 V to 2 × V

REF

Power-on reset to 0 V

Simultaneous update of DAC outputs via

LDAC

Asynchronous

CLR

facility

Low power parallel data interface

On-chip rail-to-rail output buffer amplifiers

Temperature range: −40°C to +105°C

APPLICATIONS

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

Industrial process control

GENERAL DESCRIPTION

The AD5330/AD5331/AD5340/AD5341

are single 8-/10-/12-

bit DACs. They operate from a 2.5 V to 5.5 V supply consuming

just 115 μA at 3 V and feature a power-down mode that further

reduces the current to 80 nA. The devices incorporate an on-chip

output buffer that can drive the output to both supply rails, but

the AD5330, AD5340, and AD5341 allow a choice of buffered

or unbuffered reference input.

The AD5330/AD5331/AD5340/AD5341 have a parallel

interface.

selects the device and data is loaded into the

input registers on the rising edge of

The GAIN pin allows the output range to be set at 0 V to V

REF

0 V to 2 × V

REF

Input data to the DACs is double-buffered, allowing simultane-

ous update of multiple DACs in a system using the

LDAC

pin.

An asynchronous

CLR

input is also provided, which resets the

contents of the input register and the DAC register to all zeros.

These devices also incorporate a power-on reset circuit that

ensures that the DAC output powers on to 0 V and remains

there until valid data is written to the device.

The AD5330/AD5331/AD5340/AD5341 are available in thin

shrink small outline packages (TSSOP).

Protected by U.S. Patent Number 5,969,657.

FUNCTIONAL BLOCK DIAGRAM

BUFFER

8-BIT

DAC

INPUT

INTERFACE LOGIC

POWER-DOWN

LOGIC

BUF

GAIN

CLR

LDAC

REF

OUT

PD GND

AD5330

POWER-ON

RESET

3 12

11 5

6852-001

Figure 1. AD5330

Summary of content (28 pages)

PAGE 1
2.5 V to 5.5 V, 115 μA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs AD5330/AD5331/AD5340/AD5341 FEATURES GENERAL DESCRIPTION AD5330: single 8-bit DAC in 20-lead TSSOP AD5331: single 10-bit DAC in 20-lead TSSOP AD5340: single 12-bit DAC in 24-lead TSSOP AD5341: single 12-bit DAC in 20-lead TSSOP Low power operation: 115 μA @ 3 V, 140 μA @ 5 V Power-down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin 2.5 V to 5.
PAGE 2
AD5330/AD5331/AD5340/AD5341 TABLE OF CONTENTS Features .............................................................................................. 1 Double-Buffered Interface ........................................................ 18 Applications ....................................................................................... 1 Clear Input (CLR) ...................................................................... 18 General Description .......................................................
PAGE 3
AD5330/AD5331/AD5340/AD5341 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 2 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1.
PAGE 4
AD5330/AD5331/AD5340/AD5341 1 Parameter POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V IDD (Power-Down Mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V Min B Version 2 Typ Max 2.5 Unit 5.5 V 140 115 250 200 μA μA 0.2 0.08 1 1 μA μA Conditions/Comments DACs active and excluding load currents. Unbuffered Reference, VIH = VDD, VIL = GND IDD increases by 50 μA at VREF > VDD − 100 mV.
PAGE 5
AD5330/AD5331/AD5340/AD5341 TIMING CHARACTERISTICS 1, 2, 3 VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter t1 Limit at TMIN, TMAX 0 Unit ns min Condition/Comments CS to WR setup time. t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 0 20 5 4.5 5 5 4.5 5 4.5 20 20 50 ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min CS to WR hold time. WR pulse width. Data, GAIN, BUF, HBEN setup time. Data, GAIN, BUF, HBEN hold time.
PAGE 6
AD5330/AD5331/AD5340/AD5341 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND Reference Input Voltage to GND VOUT to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature TSSOP Package Power Dissipation θJA Thermal Impedance (20-Lead TSSOP)1 θJA Thermal Impedance (24-Lead TSSOP)1 Reflow Soldering Peak Temperature Time at Peak Temperature 1 Rating −0.
PAGE 7
AD5330/AD5331/AD5340/AD5341 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VREF VDD 3 12 POWER-ON RESET AD5330 INPUT REGISTER CS 6 WR 7 CLR 9 INTERFACE LOGIC DB .. 7 20 DB0 13 DAC REGISTER 8-BIT DAC BUFFER 4 VOUT BUF 1 20 DB7 NC 2 19 DB6 VREF 3 VOUT 4 GND 5 CS 6 RESET POWER-DOWN LOGIC 11 5 PD GND Figure 3.
PAGE 8
AD5330/AD5331/AD5340/AD5341 VREF VDD 3 12 POWER-ON RESET AD5331 DB8 1 CS 6 WR 7 CLR 9 INPUT REGISTER DAC REGISTER 10-BIT DAC BUFFER 4 VOUT DB8 1 20 DB7 DB9 2 19 DB6 VREF 3 VOUT 4 GND 5 RESET CS 6 POWER-DOWN LOGIC 11 5 PD GND Figure 5. AD5331 Functional Block Diagram 06852-005 LDAC 10 18 DB5 10-BIT 17 DB4 TOP VIEW (Not to Scale) 16 DB3 AD5331 15 DB2 WR 7 14 DB1 GAIN 8 13 DB0 CLR 9 12 V DD LDAC 10 11 PD Figure 6. AD5331 Pin Configuration Table 6.
PAGE 9
AD5330/AD5331/AD5340/AD5341 VREF VDD 4 14 POWER-ON RESET AD5340 DB11 2 GAIN 10 DB .. 9 24 DB0 15 CS 8 WR 9 INTERFACE LOGIC BUF 3 CLR 11 INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER RESET 5 VOUT POWER-DOWN LOGIC 13 PD Figure 7.
PAGE 10
AD5330/AD5331/AD5340/AD5341 VREF VDD 3 12 POWER-ON RESET HBEN 1 CS 6 WR 7 LOW BYTE REGISTER 20 DB7 HBEN 1 12-BIT DAC BUFFER 4 VOUT BUF VREF 3 VOUT 4 GND RESET 5 CS 6 POWER-DOWN LOGIC 19 DB6 2 18 DB5 10-BIT 17 DB4 TOP VIEW (Not to Scale) 16 DB3 AD5341 15 DB2 14 DB1 CLR 9 GAIN 8 13 DB 0 LDAC 10 CLR 9 12 V DD 11 5 PD GND Figure 9. AD5341 Functional Block Diagram 06852-009 WR 7 LDAC 10 11 PD Figure 10. AD5341 Pin Configuration Table 8.
PAGE 11
AD5330/AD5331/AD5340/AD5341 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or INL is a measure of the maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer function. Typical INL vs. code plots can be seen in Figure 14, Figure 15, and Figure 16. OUTPUT VOLTAGE ACTUAL IDEAL POSITIVE OFFSET Gain Error This is a measure of the span error of the DAC (including any error in the gain of the buffer amplifier).
PAGE 12
AD5330/AD5331/AD5340/AD5341 Offset Error Drift This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Power-Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage.
PAGE 13
AD5330/AD5331/AD5340/AD5341 TYPICAL PERFORMANCE CHARACTERISTICS 0.3 1.0 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 0.2 DNL ERROR (LSBs) INL ERROR (LSBs) 0.5 0 0.1 0 –0.1 –0.5 0 50 100 150 200 250 CODE –0.3 06852-015 0 150 200 250 800 1000 Figure 17. AD5330 Typical DNL Plot 3 0.6 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 2 0.4 DNL ERROR (LSBs) INL ERROR (LSBs) 100 CODE Figure 14. AD5330 Typical INL Plot 1 0 –1 –2 0.2 0 –0.2 –0.4 0 200 400 500 800 1000 CODE –0.
PAGE 14
AD5330/AD5331/AD5340/AD5341 0.2 TA = 25°C VDD = 5V 0.75 GAIN ERROR 0 0.25 ERROR (%) MAX INL MAX DNL 0 MIN DNL –0.25 MIN INL –0.1 –0.2 –0.3 –0.50 –0.4 –0.75 –0.5 2 3 4 5 VREF (V) –0.6 06852-021 ERROR (LSBs) 0.50 –1.00 TA = 25°C VREF = 2V 0.1 OFFSET ERROR 0 0.75 2 3 4 5 6 VDD (V) Figure 20. AD5330 INL and DNL Error vs. VREF 1.00 1 06852-024 1.00 Figure 23. Offset Error and Gain Error vs. VDD 5 VDD = 5V VREF = 3V 5V SOURCE 4 0.
PAGE 15
AD5330/AD5331/AD5340/AD5341 300 TA = 25°C TA = 25°C VDD = 5V CH2 5V CLK IDD (µA) 200 VOUT 100 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Figure 26. Supply Current vs. Supply Voltage TIME BASE = 5µs/DIV 06852-030 0 2.5 06852-027 CH1 1V Figure 29. Half-Scale Settling (¼ to ¾ Scale Code Change) 0.5 TA = 25°C TA = 25°C VDD = 5V VREF = 2V 0.4 IDD (µA) CH1 2V VDD 0.3 0.2 VOUTA 0.1 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) TIME BASE = 200µs/DIV Figure 27. Power-Down Current vs.
PAGE 16
AD5330/AD5331/AD5340/AD5341 10 0 –10 FREQUENCY VDD = 3V VDD = 5V (dB) –20 –30 –40 90 100 110 120 130 140 150 160 170 180 190 200 IDD (µA) –60 0.01 06852-033 80 1 10 100 1k 10k FREQUENCY (kHz) Figure 32. IDD Histogram with VDD = 3 V and VDD = 5 V Figure 34. Multiplying Bandwidth (Small-Signal Frequency Response) 0.4 0.917 TA = 25°C VDD = 5V 0.916 FULL-SCALE ERROR (%FSR) 0.915 0.914 0.913 0.912 0.911 0.910 0.909 0.908 0.907 0.2 0 0.906 0.904 0.903 250ns/DIV Figure 33.
PAGE 17
AD5330/AD5331/AD5340/AD5341 THEORY OF OPERATION VREF The AD5330/AD5331/AD5340/AD5341 are single resistorstring DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits, respectively. They are written to using a parallel interface. They operate from single supplies of 2.5 V to 5.5 V and the output buffer amplifiers offer rail-to-rail output swing. The AD5330, AD5340, and AD5341 have a reference input that can be buffered to draw virtually no current from the reference source.
PAGE 18
AD5330/AD5331/AD5340/AD5341 PARALLEL INTERFACE DOUBLE-BUFFERED INTERFACE The AD5330/AD5331/AD5340/AD5341 DACs all have doublebuffered interfaces consisting of an input register and a DAC register. DAC data, BUF, and GAIN inputs are written to the input register under the control of chip select (CS) and write (WR). Access to the DAC register is controlled by the LDAC function.
PAGE 19
AD5330/AD5331/AD5340/AD5341 POWER-DOWN MODE When the PD pin is high, the DAC works normally with a typical power consumption of 140 μA at 5 V (115 μA at 3 V). In power-down mode, however, the supply current falls to 200 nA at 5 V (80 nA at 3 V) when the DAC is powered down. Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier, making it open-circuit.
PAGE 20
AD5330/AD5331/AD5340/AD5341 SUGGESTED DATABUS FORMATS The AD5341 is a 12-bit device that uses byte load, so only four bits of the high byte are actually used as data. Two of the unused bits can be used for GAIN and BUF data by connecting them to the GAIN and BUF inputs; for example, Bit 6 and Bit 7, as shown in Figure 41 and Figure 42.
PAGE 21
AD5330/AD5331/AD5340/AD5341 APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUITS The AD5330/AD5331/AD5340/AD5341 can be used with a wide range of reference voltages, especially if the reference inputs are configured to be unbuffered, in which case the devices offer full, one-quadrant multiplying capability over a reference range of 0.25 V to VDD. More typically, these devices can be used with a fixed, precision reference voltage.
PAGE 22
AD5330/AD5331/AD5340/AD5341 VDD = 5V a system, all the DACs can be updated simultaneously using a common LDAC line. A common CLR line can also be used to reset all DAC outputs to zero. 0.1µF VSOURCE EXT REF DATA INPUTS GND AD780/REF192 WITH VDD = 5V CODED ADDRESS G1 74HC139 1Y0 A1 1Y1 B1 1Y2 1Y3 DGND AD820/ OP295 POWER SUPPLY BYPASSING AND GROUNDING DATA INPUTS 06852-047 DATA INPUTS *AD5341 ONLY Figure 46.
PAGE 23
AD5330/AD5331/AD5340/AD5341 Table 11. Overview of AD53xx Parallel Devices Additional Pin Functions Part No. Singles AD5330 AD5331 AD5340 AD5341 Resolution Bits DNL No. of VREF Pins Settling Time BUF GAIN 8 10 12 12 ±0.25 ±0.5 ±1.0 ±1.0 1 1 1 1 6 μs 7 μs 8 μs 8 μs BUF BUF BUF GAIN GAIN GAIN GAIN Duals AD5332 AD5333 AD5342 AD5343 8 10 12 12 ±0.25 ±0.5 ±1.0 ±1.0 2 2 2 1 6 μs 7 μs 8 μs 8 μs BUF BUF GAIN GAIN Quads AD5334 AD5335 AD5336 AD5344 8 10 10 12 ±0.25 ±0.5 ±0.5 ±1.
PAGE 24
AD5330/AD5331/AD5340/AD5341 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 48. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 7.90 7.80 7.70 24 13 4.50 4.40 4.30 1 6.40 BSC 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 0.10 COPLANARITY 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.
PAGE 25
AD5330/AD5331/AD5340/AD5341 ORDERING GUIDE Model AD5330BRU AD5330BRU-REEL AD5330BRU-REEL7 AD5330BRUZ 1 AD5330BRUZ-REEL1 AD5330BRUZ-REEL71 AD5331BRU AD5331BRU-REEL AD5331BRU-REEL7 AD5331BRUZ1 AD5331BRUZ-REEL1 AD5331BRUZ-REEL71 AD5340BRU AD5340BRU-REEL AD5340BRU-REEL7 AD5340BRUZ1 AD5340BRUZ-REEL1 AD5340BRUZ-REEL71 AD5341BRU AD5341BRU-REEL AD5341BRU-REEL7 AD5341BRUZ1 AD5341BRUZ-REEL1 AD5341BRUZ-REEL71 1 Temperature Range –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to
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AD5330/AD5331/AD5340/AD5341 NOTES Rev.
PAGE 27
AD5330/AD5331/AD5340/AD5341 NOTES Rev.