Datasheet

AD5308/AD5318/AD5328
Rev. F | Page 6 of 28
Table 3. Timing Characteristics
1, 2, 3
A, B Version
Parameter Limit at T
MIN
, T
MAX
Unit Conditions/Comments
t
1
33 ns min SCLK cycle time
t
2
13 ns min SCLK high time
t
3
13 ns min SCLK low time
t
4
13 ns min
SYNC
to SCLK falling edge setup time; temperature range (A, B
verstion): −40°C to +105°C
15 ns min
SYNC
to SCLK falling edge setup time; temperature range (A, B
verstion): −40°C to +125°C
t
5
5 ns min Data set up time
t
6
4.5 ns min Data hold time
t
7
0 ns min
SCLK falling edge to SYNC
rising edge
t
8
50 ns min
Minimum SYNC
high time
t
9
20 ns min
LDAC
pulse width
t
10
20 ns min
SCLK falling edge to LDAC
rising edge
t
11
0 ns min
SCLK falling edge to LDAC
falling edge
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 2.
02812-002
SCLK
DIN DB15
DB0
t
1
t
2
t
8
t
3
t
4
t
5
t
6
t
9
t
11
t
7
t
10
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
LDAC
1
LDAC
2
SYNC
Figure 2. Serial Interface Timing Diagram