Datasheet

AD5308/AD5318/AD5328
Rev. F | Page 22 of 28
0.1μF
02812-042
10μF
GND
DIN
AD5308/AD5318/
AD5328
V
OUT
B
V
OUT
C
V
OUT
D
V
OUT
E
V
OUT
F
V
OUT
G
V
OUT
H
V
OUT
A
V
REF
ABCD
V
REF
EFGH
V
DD
V
DD
10kΩ
5V
REGULATOR
SCLK
SYNC
SCLK
V
DD
10kΩ
SYNC
POWER
V
DD
10kΩ
DIN
Figure 42. AD5308/AD5318/AD5328 in an Opto-Isolated Interface
DECODING MULTIPLE AD5308/AD5318/AD5328s
The
SYNC
pin on the AD5308/AD5318/AD5328 can be used in
applications to decode a number of DACs. In this application,
the DACs in the system receive the same serial clock and serial
data but only the
SYNC
to one of the devices is active at any one
time, allowing access to four channels in this 16-channel sys-
tem. The 74HC139 is used as a 2-to-4 line decoder to address
any of the DACs in the system. To prevent timing errors from
occurring, the enable input should be brought to its inactive
state while the coded-address inputs are changing state.
shows a diagram of a typical setup for decoding
multiple AD5308 devices in a system.
Figure 43
02812-043
AD5308
SCLK
DIN
V
OUT
A
V
OUT
G
V
OUT
B
V
OUT
H
SYNC
DIN
SCLK
AD5308
SCLK
DIN
V
OUT
A
V
OUT
G
V
OUT
B
V
OUT
H
SYNC
74HC139
1G 1Y0
1Y1
1Y2
1Y3
ENABLE
CODED
ADDRESS
1A
1B
AD5308
SCLK
DIN
V
OUT
A
V
OUT
G
V
OUT
B
V
OUT
H
SYNC
AD5308
SCLK
DIN
V
OUT
A
V
OUT
G
V
OUT
B
V
OUT
H
SYNC
V
CC
V
DD
DGND
Figure 43. Decoding Multiple AD5308 Devices in a System