Datasheet

AD5306/AD5316/AD5326
Rev. F | Page 4 of 24
A Version
1
B Version
1
Parameter
2
Min Typ Max Min Typ Max Unit Conditions/Comments
Short-Circuit Current 25 25 mA V
DD
= 5 V.
16 16 mA V
DD
= 3 V.
Power-Up Time 2.5 2.5 μs Coming out of power-
down mode; V
DD
= 5 V.
5 5 μs Coming out of power-
down mode; V
DD
= 3 V.
LOGIC INPUTS
(Excluding SCL, SDA)
6
Input Current ±1 ±1 μA
V
IL
, Input Low Voltage 0.8 0.8 V V
DD
= 5 V ± 10%.
0.6 0.6 V V
DD
= 3 V ± 10%.
0.5 0.5 V V
DD
= 2.5 V.
V
IH
, Input High Voltage 1.7 1.7 V V
DD
= 2.5 V to 5.5 V;
TTL and 1.8 V CMOS
compatible.
Pin Capacitance 3 3 pF
LOGIC INPUTS (SCL, SDA)
6
V
IH
, Input High Voltage 0.7 V
DD
V
DD
+ 0.3 0.7 V
DD
V
DD
+ 0.3 V SMBus compatible at
V
DD
< 3.6 V.
V
IL
, Input Low Voltage −0.3 +0.3 V
DD
−0.3 +0.3 V
DD
V SMBus compatible at
V
DD
< 3.6 V.
I
IN
, Input Leakage Current ±1 ±1 μA
V
HYST
, Input Hysteresis 0.05 V
DD
0.05 V
DD
V See Figure 20.
C
IN
, Input Capacitance 8 8 pF
Glitch Rejection 50 50 ns Input filtering suppresses
noise spikes of less than
50 ns.
LOGIC OUTPUT (SDA)
6
V
OL
, Output Low Voltage 0.4 0.4 V I
SINK
= 3 mA.
0.6 0.6 V I
SINK
= 6 mA.
Three-State Leakage Current ±1 ±1 μA
Three-State Output
Capacitance
8 8 pF
POWER REQUIREMENTS
V
DD
2.5 5.5 2.5 5.5 V
I
DD
(Normal Mode)
8
V
IH
= V
DD
and V
IL
= GND;
interface inactive.
V
DD
= 4.5 V to 5.5 V 500 900 500 900 μA All DACs in unbuffered
mode.
Buffered mode, extra
current is typically x mA
per DAC, where
x = 5 μA + V
REF
/R
DAC.
V
DD
= 2.5 V to 3.6 V 400 750 400 750 μA
I
DD
(Power-Down Mode) V
IH
= V
DD
and V
IL
= GND;
interface inactive.
V
DD
= 4.5 V to 5.5 V 0.3 1 0.3 1 μA I
DD
= 3 μA (max) during
readback on SDA.
V
DD
= 2.5 V to 3.6 V 0.09 1 0.09 1 μA I
DD
= 1.5 μA (max) during
readback on SDA.
1
Temperature range (A, B versions): −40°C to +105°C; typical at +25°C.
2
See the Terminology section.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5306 (Code 8 to 255); AD5316 (Code 28 to 1023); AD5326 (Code 115 to 4095).
5
This corresponds to x codes. x = deadband voltage/LSB size.
6
Guaranteed by design and characterization; not production tested.
7
For the amplifier output to reach its minimum voltage, the offset error must be negative; for the amplifier output to reach its maximum voltage, V
REF
= V
DD
,
the offset plus gain error must be positive.
8
Interface inactive; all DACs active. DAC outputs unloaded.