Datasheet

AD5303/AD5313/AD5323
Rev. B | Page 4 of 28
A Version
1
B Version
1
Parameter
2
Min Typ Max Min Typ Max Unit Conditions/Comments
LOGIC INPUTS
5
Input Current ±1 ±1 μA
0.8 0.8 V V
DD
= 5 V ± 10%
0.6 0.6 V V
DD
= 3 V ± 10%
Input Low Voltage, V
IL
0.5 0.5 V V
DD
= 2.5 V
2.4 2.4 V V
DD
= 5 V ± 10%
2.1 2.1 V V
DD
= 3 V ± 10%
Input High Voltage, V
IH
2.0 2.0 V V
DD
= 2.5 V
Pin Capacitance 2 3.5 2 3.5 pF
LOGIC OUTPUT (SDO)
5
V
DD
= 5 V ± 10%
Output Low Voltage 0.4 0.4 V I
SINK
= 2 mA
Output High Voltage 4.0 4.0 V I
SOURCE
= 2 mA
V
DD
= 3 V ± 10%
Output Low Voltage 0.4 0.4 V I
SINK
= 2 mA
Output High Voltage 2.4 2.4 V I
SOURCE
= 2 mA
Floating-State Leakage Current 1 1 μA DCEN = GND
Floating-State Output
Capacitance
3 3 pF DCEN = GND
POWER REQUIREMENTS
V
DD
2.5 5.5 2.5 5.5 V I
DD
specification is valid for all DAC codes
I
DD
(Normal Mode) Both DACs active and excluding load
currents
V
DD
= 4.5 V to 5.5 V 300 450 300 450 μA
V
DD
= 2.5 V to 3.6 V 230 350 230 350 μA
Both DACs in unbuffered mode;
V
IH
= V
DD
and V
IL
= GND; in buffered
mode, extra current is typically x μA
per DAC, where x = 5 μA + V
REF
/R
DAC
I
DD
(Full Power-Down)
V
DD
= 4.5 V to 5.5 V 0.2 1 0.2 1 μA
V
DD
= 2.5 V to 3.6 V 0.05 1 0.05 1 μA
1
Temperature range for Version A, Version B: −40°C to +105°C.
2
See the Terminology section.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5303 (Code 8 to Code 248); AD5313 (Code 28 to Code 995); AD5323 (Code 115 to Code 3981).
5
Guaranteed by design and characterization, not production tested.
6
In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage, V
REF
= V
DD
and offset plus gain error must be positive.