Datasheet

AD5303/AD5313/AD5323
Rev. B | Page 13 of 28
600
400
300
100
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
00472-019
I
DD
(µA)
200
500
V
DD
(V)
BOTH DACS IN GAIN-OF-TWO MODE
REFERENCE INPUTS BUFFERED
+105°C
+25°C
–40°C
Figure 19. Supply Current vs. Supply Voltage
1.0
0.9
0
0.4
0.3
0.2
0.1
0.8
0.6
0.7
0.5
BOTH DACS IN
THREE-STATE CONDITION
I
DD
(µA)
V
DD
(V)
2.7 3.2 3.7 4.2 4.7 5.2
–40°C
+25°C
+105°C
00472-020
Figure 20. Power-Down Current vs. Supply Voltage
500
400
200
100
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
00472-021
I
DD
(µA)
300
700
V
LOGIC
(V)
T
A
= 25°C
V
DD
= 5V
V
DD
= 3V
600
Figure 21. Supply Current vs. Logic Input Voltage
C
H2
CH1 1V, CH2 5V, TIME BASE = 5µs/DIV
00472-022
C
H1
V
DD
= 5V
T
A
= 25°C
CLK
V
OUT
Figure 22. Half-Scale Settling (¼ to ¾ Scale Code Change)
CH2
CH1 1V, CH2 1V, TIME BASE = 20µs/DIV
00472-023
CH1
V
OUT
A
T
A
= 25°C
V
DD
Figure 23. Power-On Reset to 0 V
CH3
CH1 1V, CH3 5V, TIME BASE = 1µs/DIV
00472-024
CH1
T
A
= 25°C
V
OUT
CLK
Figure 24. Exiting Power-Down to Midscale