Datasheet

AD5301/AD5311/AD5321
Rev. B | Page 16 of 24
READ OPERATION
When reading data back from the AD5301/AD5311/AD5321
DACs, the user must begin with an address byte after which
the DAC acknowledges that it is prepared to transmit data by
pulling SDA low. There are two different read operations. In the
case of the AD5301, the readback is a single byte that consists of
the eight data bits in the DAC register. However, in the case
of the AD5311 and AD5321, the readback consists of two bytes
that contain both the data and the power-down mode bits. The
read operations for the three DACs are shown in
Figure 32 to
Figure 34.
SCL
SDA
ACK
BY
AD5301
NO ACK
BY
MASTER
START
COND
BY
MASTER
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
ADDRESS BYTE
00011
A1* A0 R/W
STOP
COND
BY
MASTER
DATA BYTE
D7 D6 D5 D4 D3 D2 D1 D0
00927-030
Figure 32. AD5301 Readback Sequence
SCL
SDA
SCL
SDA
LEAST SIGNIFICANT CONTROL BYTE
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
NO ACK
BY
MASTER
STOP
COND
BY
MASTER
PD1XX PD0 D9 D8 D7 D60A1*A00011 R/W
D5 D4 D3 D2 D1 D0 X X
ACK
BY
AD5311
ACK
BY
AD5311
START
COND
BY
MASTER
MOST SIGNIFICANT BYTEADDRESS BYTE
00927-031
Figure 33. AD5311 Readback Sequence
LEAST SIGNIFICANT BYTE
SCL
SD
A
SCL
SD
A
ACK
BY
AD5321
NO ACK
BY
MASTER
START
COND
BY
MASTER
STOP
COND
BY
MASTER
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
ADDRESS BYTE
STOP
COND
BY
MASTER
MOST SIIGNIFICANT BYTE
0
D7 D6 D5 D4 D3 D2 D1 D0
0011
A1* A0 R/W
X X PD1 PD0 D11 D10 D9 D8
00927-032
Figure 34. AD5321 Readback Sequence