Datasheet

AD5320
Rev. C | Page 4 of 20
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Limit at T
MIN
, T
MAX
Parameter
1, 2
V
DD
= 2.7 V to 3.6 V V
DD
= 3.6 V to 5.5 V Unit Description
t
1
3
50 33 ns min SCLK cycle time
t
2
13 13 ns min SCLK high time
t
3
22.5 13 ns min SCLK low time
t
4
0 0 ns min
SYNC to SCLK rising edge setup time
t
5
5 5 ns min Data setup time
t
6
4.5 4.5 ns min Data hold time
t
7
0 0 ns min
SCLK falling edge to
SYNC rising edge
t
8
50 33 ns min
Minimum
SYNC high time
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
See Figure 2.
3
Maximum SCLK frequency is 30 MHz at V
DD
= 3.6 V to 5.5 V and 20 MHz at V
DD
= 2.7 V to 3.6 V.
00934-002
SCLK
DIN
DB15
DB0
t
4
t
1
t
3
t
2
t
8
t
7
t
6
t
5
SYNC
Figure 2. Serial Write Operation