Datasheet

AD5310 Data Sheet
Rev. B | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. SOT-23
Figure 4. µSOIC
Table 4. SOT-23 Pin Function Descriptions
Pin No. Mnemonic Description
1 V
OUT
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
2 GND Ground Reference Point for All Circuitry on the Part.
3 V
DD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and V
DD
should be decoupled to GND.
4 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input.
5
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 30 MHz.
6
SYNC
Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.
When
SYNC
goes low, it enables the input shift register, and data is transferred in on the falling edges of the
following clocks. The DAC is updated following the 16th clock cycle unless
SYNC
is taken high before this edge,
in which case the rising edge of
SYNC
acts as an interrupt and the write sequence is ignored by the DAC.