Datasheet

AD5307/AD5317/AD5327
Rev. C | Page 6 of 28
2mA I
OL
2mA I
OH
V
OH (MIN)
TO OUTPUT
PIN
C
L
50pF
02067-002
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
02067-003
SCLK
DIN
DB15
DB0
t
4
t
1
t
3
t
2
t
8
t
7
t
9
t
12
t
10
t
11
t
6
t
5
LDAC
1
LDAC
2
CLR
SYNC
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
Figure 3. Serial Interface Timing Diagram
SCLK
DIN
DB15
DB0 DB15' DB0'
DB0
SDO
INPUT WORD FOR DAC N INPUT WORD FOR DAC (N+1)
UNDEFINED INPUT WORD FOR DAC N
DB15
t
1
SYNC
LDAC
t
2
t
3
t
4
t
5
t
6
t
8
t
9
t
13
t
14
t
15
t
16
02067-004
Figure 4. Daisy-Chaining Timing Diagram